Abstract: Testing an integrated circuit (IC) that has a set of nominally similar cores and pairs of test data input (TDI) and test data output (TDO) pads common to the different cores. Similar scan chains in parallel in the different cores provide response signals as functions of corresponding TDI signals. Respective combined TDO signals are provided to the TDO pads. In the absence of a defect, the combined TDO signals are asserted and de-asserted like the response signals from corresponding chains in the different cores and like corresponding expected response signals. The combined TDO signals are different from the corresponding expected response signals in the presence of a defect in at least one of the cores. If the result is a fail, the ATE may identify a defective core using a diagnosis module in the IC providing response signals from a selected core.

Abstract: Testing an integrated circuit (IC) that has a set of nominally similar cores and pairs of test data input (TDI) and test data output (TDO) pads common to the different cores. Similar scan chains in parallel in the different cores provide response signals as functions of corresponding TDI signals. Respective combined TDO signals are provided to the TDO pads. In the absence of a defect, the combined TDO signals are asserted and de-asserted like the response signals from corresponding chains in the different cores and like corresponding expected response signals. The combined TDO signals are different from the corresponding expected response signals in the presence of a defect in at least one of the cores. If the result is a fail, the ATE may identify a defective core using a diagnosis module in the IC providing response signals from a selected core.