Patents by Inventor Zhiyong Li

Zhiyong Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Amorphous metal alloy electrodes in non-volatile device applications
    Patent number: 10177310
    Abstract: A non-volatile memory device includes two electrodes and an active region disposed between and in electrical contact with the electrodes. The active region contains a switching material capable of carrying a species of dopants and transporting the dopants under an electrical field. The electrode is an amorphous conductive material comprising 5 to 90 at % of a first metal, 5 to 90 at % of a second metal, and 5 to 90 at % of a metalloid, wherein the metalloid is any of carbon, silicon, and boron. The metalloid, the first metal, and the second metal account for at least 70 at % of the amorphous conductive material.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: January 8, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gary Gibson, James Elmer Abbott, Jr., Zhiyong Li
  • MEMRISTOR CROSSBAR ARRAY FOR PERFORMING A FOURIER TRANSFORMATION
    Publication number: 20180373675
    Abstract: A technique includes providing a first set of values to a memristor crossbar array and using the memristor crossbar array to perform a Fourier transformation. Using the memristor crossbar array to perform the Fourier transform includes using the array to apply a Discrete Fourier Transform (DFT) to the first set of values to provide a second set of values.
    Type: Application
    Filed: January 28, 2016
    Publication date: December 27, 2018
    Applicant: Hewlett Packard Enterprise Development LP
    Inventors: John Paul Strachan, Miao Hu, R. Stanley Williams, Zhiyong Li
  • Dynamic logic memcap
    Patent number: 10162263
    Abstract: An integrated circuit may include a substrate with a plurality of transistors formed in the substrate. The plurality of transistors may be coupled to a first metal layer formed over the plurality of transistors. A plurality of high dielectric nanometer capacitors may be formed of memristor switch material between the first metal layer and a second metal layer formed over the plurality of high dielectric capacitors. The plurality of high dielectric capacitors may operate as memory storage cells in dynamic logic.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: December 25, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Zhiyong Li, Jianhua Yang, R. Stanley Williams
  • Techniques for decentralized load balancing
    Patent number: 10157085
    Abstract: Various embodiments are generally directed to decentralized load balancing in a host cluster utilized to coordinate performance of processing tasks in a workload, such as via service agents and/or host instances included in the host cluster, for instance. Some embodiments are particularly directed to a set of service agents on one or more host instances that utilize a shared cache to coordinate among themselves to automatically balance a workload without a centralized controller or a centralized load balancer. In one or more embodiments, a set of service agents may automatically and cooperatively balance a workload among themselves using the shared cache.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 18, 2018
    Assignee: SAS INSTITUTE INC.
    Inventors: Qing Gong, Shianchin “Sam” Chen, Zhiyong Li
  • CROSSBAR ARRAYS FOR CALCULATING MATRIX MULTIPLICATION
    Publication number: 20180350433
    Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections, and a plurality of diagonal control lines coupled to the plurality of junctions. Each junction comprises a resistive memory element and a transistor, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
    Type: Application
    Filed: September 25, 2015
    Publication date: December 6, 2018
    Inventors: Miao Hu, Zhiyong Li, John Paul Strachan
  • SILOXANE-CONTAINING SOLAR CELL METALLIZATION PASTES
    Publication number: 20180351011
    Abstract: Frontside metallization pastes for solar cell electrodes contain siloxanes. Metallization pastes containing siloxanes can be used to fabricate fine line, high aspect ratio, solar cell gridlines.
    Type: Application
    Filed: August 13, 2018
    Publication date: December 6, 2018
    Inventors: Mohamed M. Hilali, Zhang Wei, Zhiyong Li
  • Techniques for decentralized load balancing
    Patent number: 10146593
    Abstract: Various embodiments are generally directed to decentralized load balancing in a host cluster utilized to coordinate performance of processing tasks in a workload, such as via service agents and/or host instances included in the host cluster, for instance. Some embodiments are particularly directed to a set of service agents on one or more host instances that utilize a shared cache to coordinate among themselves to automatically balance a workload without a centralized controller or a centralized load balancer. In one or more embodiments, a set of service agents may automatically and cooperatively balance a workload among themselves using the shared cache.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 4, 2018
    Assignee: SAS INSTITUTE INC.
    Inventors: Qing Gong, Shianchin “Sam” Chen, Zhiyong Li
  • CROSSBAR ARRAYS FOR CALCULATING MATRIX MULTIPLICATION
    Publication number: 20180301189
    Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, and a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections. Each junction comprises a resistive memory element, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
    Type: Application
    Filed: August 7, 2015
    Publication date: October 18, 2018
    Inventors: Miao Hu, John Paul Strachan, Zhiyong Li, R. Stanley Williams
  • Integrated circuit devices comprising memristors
    Patent number: 10076904
    Abstract: In some examples, an integrated circuit device includes a substrate, a memristor over the substrate and comprising a first metal layer as a first electrode, a second metal layer as a second electrode, and a switching oxide layer between the first and second metal layers, and a thermal resistor layer over the substrate.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 18, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Jianhua Yang, Ning Ge, Zhiyong Li
  • Siloxane-containing solar cell metallization pastes
    Patent number: 10079318
    Abstract: Frontside metallization pastes for solar cell electrodes contain siloxanes. Metallization pastes containing siloxanes can be used to fabricate fine line, high aspect ratio, solar cell gridlines.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: September 18, 2018
    Assignee: Zhejiang Kaiying New Materials Co., Ltd.
    Inventors: Mohamed M. Hilali, Zhang Wei, Zhiyong Li
  • Sensing a property of a fluid
    Patent number: 10071552
    Abstract: In an example, a device for sensing a property of a fluid may include an ion-sensitive field effect transistor (ISFET) having a gate, a source, and a drain. The device may also include a first metal element in contact with the gate and a switching layer in contact with the first metal layer. A resistance state of the switching layer is to be modified through application of an electrical field of at least a predefined strength through the switching layer and is to be retained in the switching layer following removal of the electrical field. The device may also include a metal plate in contact with the switching layer, in which the metal plate is to directly contact the fluid for which the property is to be sensed.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: September 11, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Zhiyong Li, Leong Yap Chia, Wai Mun Wong
  • Negative differential resistance (NDR) device based on fast diffusive metal atoms
    Patent number: 10074695
    Abstract: A negative differential resistance (NDR) device for non-volatile memory cells in crossbar arrays is provided. Each non-volatile memory cell is situated at a crosspoint of the array. Each non-volatile memory cell comprises a switching layer in series with an NDR material containing fast diffusive atoms that are electrochemically inactive. The switching layer is positioned between two elec-trodes.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: September 11, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jianhua Yang, Stanley Williams, Max Zhang, Zhiyong Li
  • Polarization selective surface enhanced raman spectroscopy
    Patent number: 10067060
    Abstract: Polarization selective surface enhanced Raman spectroscopy (SERS) includes a plurality of nanofingers arranged as a SERS multimer to exhibit a polarization-dependent plasmonic mode and one or both of a stimulus source and a Raman detector. The stimulus source is to illuminate the SERS multimer with a stimulus signal and the Raman detector is to detect a Raman scattering signal emitted by an analyte in a vicinity of the SERS multimer. One or both of the Raman scattering signal has a polarization state dictated by or associated with the polarization-dependent plasmonic mode and the stimulus signal has a polarization state corresponding to the polarization-dependent plasmonic mode.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: September 4, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gary Gibson, Huei Pei Kuo, Steven J. Barcelo, Zhiyong Li
  • TECHNIQUES FOR DECENTRALIZED LOAD BALANCING
    Publication number: 20180239650
    Abstract: Various embodiments are generally directed to decentralized load balancing in a host cluster utilized to coordinate performance of processing tasks in a workload, such as via service agents and/or host instances included in the host cluster, for instance. Some embodiments are particularly directed to a set of service agents on one or more host instances that utilize a shared cache to coordinate among themselves to automatically balance a workload without a centralized controller or a centralized load balancer. In one or more embodiments, a set of service agents may automatically and cooperatively balance a workload among themselves using the shared cache.
    Type: Application
    Filed: December 22, 2017
    Publication date: August 23, 2018
    Applicant: SAS Institute Inc.
    Inventors: Qing Gong, Shianchin "Sam" Chen, Zhiyong Li
  • TECHNIQUES FOR DECENTRALIZED LOAD BALANCING
    Publication number: 20180239651
    Abstract: Various embodiments are generally directed to decentralized load balancing in a host cluster utilized to coordinate performance of processing tasks in a workload, such as via service agents and/or host instances included in the host cluster, for instance. Some embodiments are particularly directed to a set of service agents on one or more host instances that utilize a shared cache to coordinate among themselves to automatically balance a workload without a centralized controller or a centralized load balancer. In one or more embodiments, a set of service agents may automatically and cooperatively balance a workload among themselves using the shared cache.
    Type: Application
    Filed: December 22, 2017
    Publication date: August 23, 2018
    Applicant: SAS Institute Inc.
    Inventors: Qing Gong, Shianchin "Sam" Chen, Zhiyong Li
  • Generating a representative logic indicator of grouped memristors
    Patent number: 10056142
    Abstract: A device for generating a representative logic indicator of grouped memristors is described. The device includes a memristor array. The memristor array includes a number of first memristors having a first set of logic indicators and a number of second memristors having a second set of logic indicators. The second set of logic indicators is different than the first set of logic indicators. Each first memristor is grouped with a corresponding second memristor during a memory read operation to generate a representative logic indicator.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: August 21, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Jianhua Yang, Zhiyong Li, R. Stanley Williams
  • Method and device for generating digital signature
    Patent number: 10038561
    Abstract: Disclosed are a method and device for generating a digital signature. The method comprises: a device generating a digital signature parameter r that meets an effective determining condition; generating a digital signature parameter s according to the following formula s=((1+dA)?1·(r+k)?r)mod n, by using a private key dA, a random number k, r, and an elliptic curve parameter n, a value range of k being [1, n?1]; determining if the generated s is 0; if s is 0, regenerating r that meets the effective determining condition, and regenerating s by using dA, the regenerated k with the value range of [1, n?1] and the regenerated r and n, until s is not 0; converting data types of r and s that is not 0 into byte strings, to obtain a digital signature (r, s).
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: July 31, 2018
    Assignee: CHINA IWNCOMM CO., LTD.
    Inventors: Zhiyong Li, Hongtao Wan, Xiang Yan
  • Multilayered memristors
    Patent number: 10026896
    Abstract: A multilayered memristor includes a semiconducting n-type layer, a semiconducting p-type layer, and a semiconducting intrinsic layer. The semiconducting n-type layer includes one or both of anion vacancies and metal cations. The semiconducting p-type layer includes one or both of metal cation vacancies and anions. The semiconducting intrinsic layer is coupled between the n-type layer and the p-type layer to form an electrical series connection through the n-type layer, the intrinsic layer, and the p-type layer.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: July 17, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Warren Jackson, Jianhua Yang, Kyung Min Kim, Zhiyong Li
  • Memristors with oxide switching layers
    Patent number: 10026894
    Abstract: An example memristor includes a first conductive layer, a switching layer, and a second conductive layer. The first conductive layer may include a first conductive material and a second conductive material. The second conductive material may have a higher diffusivity than the first conductive material. The switching layer may be coupled to the first conductive layer and may include a first oxide having the first conductive material and a second oxide having the second conductive material. The second conductive layer may be coupled to the switching layer.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: July 17, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Jianhua Yang, Zhiyong Li, Minxian Zhang, Katy Samuels
  • COOLANT LEAK DETECTION BASED ON A NANOSENSOR RESISTANCE MEASUREMENT
    Publication number: 20180188133
    Abstract: Examples herein relate to detecting a coolant leak. For example, a system includes a nanosensor coupled to an airflow channel in a server. The nanosensor provides a resistance measurement to a controller. The system includes the controller coupled to the nanosensor. The controller detects the coolant leak based on the resistance measurement from the nanosensor.
    Type: Application
    Filed: January 4, 2017
    Publication date: July 5, 2018
    Inventors: Tahir Cader, Zhiyong Li, John Franz