Patents by Inventor Zhiyong Ma

Zhiyong Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967874
    Abstract: The present disclosure discloses a linear motor including a housing with an accommodation space, a vibrator and a stator received in the accommodation space and an elastic support fixed on the vibrator and configured to suspend the vibrator in the accommodation space; the stator includes a coil and a copper ring both opposite to the vibrator; the copper ring and the coil are arranged on two opposite sides of the vibrator separately along a first direction perpendicular with a vibration direction of the vibrator. The copper ring serves as a damper providing electromagnetic resilience for the vibrator, effectively improve the automation and efficiency of the manufacture of the linear vibration motor.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: April 23, 2024
    Assignee: AAC Microtech (Changzhou) Co., Ltd.
    Inventors: Ziang Li, Zhiyong Cui, Jie Ma, Lubin Mao
  • Publication number: 20240116950
    Abstract: Provided are small molecule inhibitors of the KRAS(G12D) mutant oncoprotein having the structural formula: and pharmaceutically acceptable salts and compositions thereof, which are useful for treating cancers and related conditions.
    Type: Application
    Filed: September 8, 2023
    Publication date: April 11, 2024
    Inventors: Weiwen Ying, Chenghao Ying, Kevin P. Foley, Zhiyong Wang, Wei Yin, Liang Ma, Guoqiang Wang, Jinhua Li, Yaya Wang, Yan Dai, Thomas Prince
  • Patent number: 11949307
    Abstract: The present disclosure discloses a linear motor having a housing with an accommodation space, a vibration unit and a driving unit received in the accommodation. The vibrator unit includes a weight with a receiving space and a magnet unit fixed on the weight and inside the receiving space. The driving unit includes an iron core received in the receiving space, two pole pieces respectively fixed on two opposite ends of the iron core along a vibration direction and a coil wound around the iron core. A groove is provided on the pole piece and faces the magnet unit along a first direction perpendicular with the vibration direction. The distance between the pole piece and the magnet unit increases, effectively decreasing the magnetic attraction force between the pole piece and magnet unit and avoiding the non-linear vibration of the linear vibration motor.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: April 2, 2024
    Assignee: AAC Microtech (Changzhou) Co., Ltd.
    Inventors: Ziang Li, Lubin Mao, Zhiyong Cui, Jie Ma
  • Patent number: 11916458
    Abstract: One of the objects of the present disclosure is to provide a linear vibration motor which improves the rigidity of the whole system and ensures enhanced stability. The present disclosure provides a linear vibration motor having a housing body; a stator including at least two solenoid assemblies with parallel axes; a vibrator installed in the housing body; and an elastic connector suspending the vibrator in the housing body. The vibrator includes a first magnet assembly being located between two adjacent at least two solenoid assemblies and including a first magnet and a second magnet. Magnetization directions of the first magnet and the second magnet are opposite and parallel to an axial direction of the solenoid assembly.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: February 27, 2024
    Assignee: AAC Microtech (Changzhou) Co., Ltd.
    Inventors: Zhiyong Cui, Yao Wang, Lubin Mao, Yun Tang, Jie Ma
  • Publication number: 20230317408
    Abstract: Pulsed beam prober systems, devices, and techniques are described herein related to providing a beam detection frequency that is less than a electrical test frequency. An electrical test signal at the electrical test frequency is provided to die under test. A pulsed beam is applied to the die such that the pulsed beam has packets of beam pulses or a frequency delta with respect to the electrical test frequency. The packets of beam pulses or the frequency delta elicits a detectable beam modulation in an imaging signal reflected from the die such that the imaging signal is modulated at a detection frequency less than the electrical test frequency.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Applicant: Intel Corporation
    Inventors: Xianghong Tong, Martin Von Haartman, Wen-Hsien Chuang, Zhiyong Ma, Hyuk Ju Ryu, Prasoon Joshi, May Ling Oh, Jennifer Huening, Shuai Zhao, Charles Peterson, Ira Jewell, Hasan Faraby
  • Publication number: 20230305057
    Abstract: Wafer level electron beam prober systems, devices, and techniques, are described herein related to providing wafer level testing for fabricated device structures. Such wafer level testing contacts a first side of a die of a wafer with a probe to provide test signals to the die under test and performs e-beam imaging of the first side of the die while the test signals are provided to the die under test.
    Type: Application
    Filed: March 22, 2022
    Publication date: September 28, 2023
    Applicant: Intel Corporation
    Inventors: Xianghong Tong, Martin Von Haartman, Zhiyong Ma, Jennifer J. Huening, Hyuk Ju Ryu, Christopher Morgan, Shuai Zhao, Ramune Nagisetty, Tuyen K. Tran, Wen-Hsien Chuang
  • Patent number: 11749560
    Abstract: Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: September 5, 2023
    Assignee: Intel Corporation
    Inventors: Thomas Marieb, Zhiyong Ma, Miriam R. Reshotko, Christopher Jezewski, Flavio Griggio, Rahim Kasim, Nikholas G. Toledo
  • Publication number: 20210079596
    Abstract: The present invention disclosed a wall-cloth with a laminated core coated through infiltration, a method for making the same and a method for an object, wherein, the wall-cloth comprises a prime coating layer, a laminated core complex covered on the prime coating layer; wherein the laminated core complex comprises a second coating layer which can be transparent or semi-transparent and a fiber sheet encapsulated in the second coating layer; and wherein, the fiber sheet possesses a network structure formed by fiber or fibers, and the second coating layer permeates into the meshes of the network structure. According to the present invention, the texture is controlled, because the fiber sheet can be produced according to a standard and large scale method to obtain identical texture. Meanwhile, the wall-cloth made by the present invention has excellence breathability and great gas transmission.
    Type: Application
    Filed: December 30, 2018
    Publication date: March 18, 2021
    Applicant: SUZHOU HONGNI NEW-MATERIAL TECHNOLOGY LTD., CO.
    Inventor: Zhiyong Ma
  • Publication number: 20200098619
    Abstract: Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Applicant: INTEL CORPORATION
    Inventors: Thomas Marieb, Zhiyong Ma, Miriam R. Reshotko, Christopher Jezewski, Flavio Griggio, Rahim Kasim, Nikholas G. Toledo
  • Publication number: 20180145083
    Abstract: The controlled modification of an antifuse programming voltage is described. In one example, an antifuse circuit is formed on a substrate, including a gate area of the antifuse circuit. A molecule is implanted into the gate area to damage the structure of the gate area. Electrodes are formed over the gate areas to connect the antifuse circuit to other components.
    Type: Application
    Filed: June 25, 2015
    Publication date: May 24, 2018
    Inventors: Xiaoghong TONG, Walid M. HAFEZ, Zhiyong MA, Peng BAI, Chia-Hong JAN, Zhanping CHEN
  • Patent number: 9123724
    Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
  • Publication number: 20140103448
    Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
    Type: Application
    Filed: December 19, 2013
    Publication date: April 17, 2014
    Inventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
  • Patent number: 8618613
    Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: December 31, 2013
    Assignee: Intel Corporation
    Inventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
  • Publication number: 20120248546
    Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Inventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
  • Patent number: 8242831
    Abstract: A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: August 14, 2012
    Assignee: Intel Corporation
    Inventors: Xianghong Tong, Zhanping Chen, Kevin X. Zhang, Zhiyong Ma, Kevin D. Johnson, Jun He
  • Publication number: 20110156801
    Abstract: A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Inventors: Xianghong Tong, Zhanping Chen, Kevin X. Zhang, Zhiyong Ma, Kevin D. Johnson, Jun He
  • Patent number: 7679145
    Abstract: A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the performance of at least a portion of the MOS devices on the die.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 16, 2010
    Assignee: Intel Corporation
    Inventors: Jun He, Zhiyong Ma, Jose A. Maiz, Mark Bohr, Martin D. Giles, Guanghai Xu
  • Publication number: 20060043579
    Abstract: A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the performance of at least a portion of the MOS devices on the die.
    Type: Application
    Filed: August 31, 2004
    Publication date: March 2, 2006
    Inventors: Jun He, Zhiyong Ma, Jose Maiz, Mark Bohr, Martin Giles, Guanghai Xu
  • Patent number: 6878465
    Abstract: The present invention describes a method including providing a component, the component having a bond pad; forming a passivation layer over the component; forming a via in the passivation layer to uncover the bond pad; and forming an under bump metallurgy (UBM) over the passivation layer, in the via, and over the bond pad, in which the UBM includes an alloy of Aluminum and Magnesium. The present invention also describes an under bump metallurgy (UBM) that includes a lower layer, the lower layer including an alloy of Aluminum and Magnesium; and an upper layer located over the lower layer.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: April 12, 2005
    Assignee: Intel Corporation
    Inventors: Peter K. Moon, Zhiyong Ma, Madhav Datta
  • Patent number: 6740427
    Abstract: The invention relates to a ball limiting metallurgy stack for an electrical device that contains a tin diffusion barrier and thermo-mechanical buffer layer disposed upon a refractory metal first layer. The multi-diffusion barrier layer stack resists tin migration toward the upper metallization of the device.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: May 25, 2004
    Assignee: Intel Corporation
    Inventors: Madhav Datta, Dave Emory, Tzeun-luh Huang, Subhash M. Joshi, Christine A. King, Zhiyong Ma, Thomas Marieb, Michael Mckeag, Doowon Suh, Simon Yang