Patents by Inventor Zhiyong Zhang
Zhiyong Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230262845Abstract: Systems and methods for flash joule heating carbon with variable frequency drives, for the production of graphene. The system includes a flash joule heating system, and a variable frequency drive system for driving the flash joule heating system, wherein the variable frequency drive system is coupled to the flash joule heating system, and is configured to output a pulse-width modulated current. The system and methods may further include sample temperature feedback, to adjust the output of variable frequency drive system.Type: ApplicationFiled: February 14, 2023Publication date: August 17, 2023Inventors: James Mitchell Tour, Duy X Luong, Carter Kittrell, Tyler Cooksey, Zhiyong Zhang, Vladimir Mancevski
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Publication number: 20230244322Abstract: Embodiments of the present disclosure relate to a display apparatus. The display apparatus includes: a display; a user interface; and a controller, configured to perform: in response to a user input, synchronizing menu content data set under a current source to other sources, so that the other sources can obtain the same display effect as that under the current source. Unnecessary repeated setting is avoided, and convenience is brought to users in use.Type: ApplicationFiled: April 7, 2023Publication date: August 3, 2023Inventor: Zhiyong ZHANG
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Patent number: 11650669Abstract: Embodiments of the present disclosure relate to a display apparatus. The display apparatus includes: a display; a user interface; and a controller, configured to perform: in response to a user input, synchronizing menu content data set under a current source to other sources, so that the other sources can obtain the same display effect as that under the current source. Unnecessary repeated setting is avoided, and convenience is brought to users in use.Type: GrantFiled: November 24, 2021Date of Patent: May 16, 2023Assignee: HISENSE VISUAL TECHNOLOGY CO., LTD.Inventor: Zhiyong Zhang
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Publication number: 20230080214Abstract: The present invention provides a system and method for analysis of integrated circuit testing anomalies based on deep learning. Through repeated training by deep learning with historical test data accumulated during testing, automatic optimization of parameter settings depending on learning and training conditions is made possible. Moreover, based on real-time test data, testing anomalies can be predicted and early warnings against them can be provided to allow advanced intervention for preventing their occurrence. Additionally, for testing anomalies that have occurred, solutions can be automatically identified and provided, which shorten the times taken by different technicians to address the anomalies, resulting in more effective utilization of the equipment and lower testing cost.Type: ApplicationFiled: August 31, 2021Publication date: March 16, 2023Inventors: Kun YU, Zhiyong ZHANG, Jianhua QI, Yi WU, Yongjia WU, Yong NIU
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Patent number: 11558343Abstract: Provided are a method and an apparatus for resolving a domain name based on a co-governance chain. The method includes: determining data distribution nodes, and constructing a root domain name co-governance chain based on the data distribution nodes; obtaining trusted root zone data based on the root domain name co-governance chain, and constructing a co-governance root service based on the trusted root zone data; and resolving a domain name by applying a recursive resolution mode based on the co-governance root service and corresponding data in the root domain name co-governance chain, in response to receiving a domain name resolution request. With the root domain name co-governance chain, a decentralized processing mode is used, nodes are equal, and it is only required to make an adjustment in a certain node upon resolving a domain name, thereby avoiding risks such as single point management and centralization.Type: GrantFiled: October 15, 2020Date of Patent: January 17, 2023Assignee: CHINA INTERNET NETWORK INFORMATION CENTERInventors: Yu Zeng, Hongtao Li, Anlei Hu, Kejun Dong, Zhiwei Yan, Xue Yang, Haikuo Zhang, Zhiyong Zhang
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Publication number: 20220355524Abstract: The present disclosure relates to a wood-plastic coated metal composite profile and a production process, and belongs to the technical field of composite profiles. The wood-plastic coated metal composite profile includes a metal core material, a wood-plastic surface layer and an intermediate layer provided between the metal core material and the wood-plastic surface layer. The intermediate layer includes unsaturated carboxylic acid modified polyolefin and thermoplastic polyurethane elastomer, inorganic filler, polyurethane prepolymer. In the present disclosure, an intermediate layer is provided between the wood-plastic surface layer and the metal core material for bonding. The intermediate layer has excellent performance when bonding with the metal, and at the same time, it can blend with the wood-plastic surface layer to a certain extent during co-extrusion.Type: ApplicationFiled: May 24, 2021Publication date: November 10, 2022Inventors: Daoyuan Tang, Guangrong Wu, Zhiyong Zhang
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Patent number: 11364135Abstract: A stent comprising a stent body and a plurality of cells is disclosed. Each cell includes two structural members extending in an undulating pattern. Each structural member includes a plurality of cell segments defining a plurality of peaks and valleys therebetween. A first segment and a second segment defining a first peak, the second segment and a third segment defining a first valley, the third segment and a fourth segment defining a second peak, the fourth segment and a fifth segment defining a second valley, the fifth segment and a sixth segment defining a third peak. The first peak, the second peak and the first valley include a first radius of curvature. The third peak and the second valley include a second radius of curvature. The first radius of curvature is larger than the second radius of curvature.Type: GrantFiled: June 22, 2018Date of Patent: June 21, 2022Assignee: COVIDIEN LPInventors: Jeffrey H. Vogel, Paul Noffke, Zhiyong Zhang
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Patent number: 11336554Abstract: The invention relates to a universal semiconductor automatic high-speed serial signal testing method, comprising: a chip to be tested sending, to an impedance matching unit, a high-speed serial signal; then by means of a phase shift unit, sequentially transforming, according to a set fixed resolution, the phase of the high-speed serial signal, the magnitude of each offset phase being determined by a phase shift control signal outputted by a control unit and the resolution of the phase shift unit; after passing through the phase shift unit, the high-speed serial signal keeps channel impedance matching by means of the impedance matching unit; the signal entering an acquisition unit, and being acquired under the action of an acquisition control signal sent by the control unit; the control unit performing signal exchange with semiconductor automatic testing equipment (ATE); and the acquisition unit transmitting the acquired signal back to the universal semiconductor ATE for algorithm operation, and then the actuaType: GrantFiled: June 8, 2018Date of Patent: May 17, 2022Assignee: SINO IC TECHNOLOGY CO., LTD.Inventors: Kun Yu, Zhiyong Zhang, Hua Wang, Jianhua Qi, Bin Luo
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Publication number: 20220104131Abstract: A Bluetooth-based data transmission method is provided. The method is applied on a first device and includes the following steps: establishing a communication connection with a second device; determining a sniff interval which comprises a sniff wake-up window; entering a sniff mode; and transmitting a first data packet to the second device in the sniff interval. The transmission duration of the first data packet is longer than or equal to two time slots. The step of transmitting the first data packet to the second device in the sniff interval includes the steps of starting to transmit the first data packet to the second device in an even time slot of the sniff interval or in an odd time slot of the sniff interval. With the data transmission method of the present application, synchronization between transmission of the first device and reception of the second device can be realized.Type: ApplicationFiled: September 29, 2021Publication date: March 31, 2022Inventors: Yili WANG, Zhiyong ZHANG, Enhong ZHU
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Publication number: 20220103512Abstract: Provided are a method and an apparatus for resolving a domain name based on a co-governance chain. The method includes: determining data distribution nodes, and constructing a root domain name co-governance chain based on the data distribution nodes; obtaining trusted root zone data based on the root domain name co-governance chain, and constructing a co-governance root service based on the trusted root zone data; and resolving a domain name by applying a recursive resolution mode based on the co-governance root service and corresponding data in the root domain name co-governance chain, in response to receiving a domain name resolution request. With the root domain name co-governance chain, a decentralized processing mode is used, nodes are equal, and it is only required to make an adjustment in a certain node upon resolving a domain name, thereby avoiding risks such as single point management and centralization.Type: ApplicationFiled: October 15, 2020Publication date: March 31, 2022Applicant: CHINA INTERNET NETWORK INFORMATION CENTERInventors: Yu ZENG, Hongtao LI, Anlei HU, Kejun DONG, Zhiwei YAN, Xue YANG, Haikuo ZHANG, Zhiyong ZHANG
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Publication number: 20220083146Abstract: Embodiments of the present disclosure relate to a display apparatus. The display apparatus includes: a display; a user interface; and a controller, configured to perform: in response to a user input, synchronizing menu content data set under a current source to other sources, so that the other sources can obtain the same display effect as that under the current source. Unnecessary repeated setting is avoided, and convenience is brought to users in use.Type: ApplicationFiled: November 24, 2021Publication date: March 17, 2022Inventor: Zhiyong ZHANG
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Patent number: 11194233Abstract: The present disclosure relates to a stand. The stand may include a supporting component, a rotation component, a rotation limiting component, and an adapter ring. The rotation component may be rotatably connected to the supporting component and may be configured to rotate about a first rotation axis. The adapter ring may be placed between the rotation component and the rotation limiting component. The rotation component may include first ratchet teeth on a first side of the rotation component. The rotation limiting component may include second ratchet teeth on a second side of the rotation limiting component facing the first side. The adapter ring may include third ratchet teeth and fourth ratchet teeth on a third side and a fourth side of the adapter ring, respectively. The third ratchet teeth may be engaged with the first ratchet teeth and the fourth ratchet teeth may be engaged with the second ratchet teeth.Type: GrantFiled: September 2, 2020Date of Patent: December 7, 2021Assignee: ZHEJIANG DAHUA TECHNOLOGY CO., LTD.Inventors: Liang Dong, Zhengchun Luo, Zhiyong Zhang
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Patent number: 11107900Abstract: A dual-gate transistor and its production method are disclosed. An auxiliary gate is connected to the power supply of the integrated circuits, to form thick and high square-shaped potential barrier of minority carriers adjacent to the drain electrode, while the potential barrier is transparent for the majority carriers from the source electrodes. The potential barrier can effectively inhibit reverse minority carrier tunneling from the drain electrode at large drain-source voltage. The transistor can be easily turned on at small drain-source voltage, without significantly decreasing the on-state current. The dual-gate transistor can significantly suppress ambipolar behavior with increased current on/off ratio and reduced power consumption, and maintain the high performance. Based on transistors, strengthened CMOS circuits can have high noise margin, low voltage loss, reduced logic errors, high performance and low power consumption.Type: GrantFiled: April 21, 2020Date of Patent: August 31, 2021Assignee: Peking UniversityInventors: Chenyi Zhao, Donglai Zhong, Zhiyong Zhang, Lianmao Peng
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Patent number: 10977469Abstract: The present invention discloses a halo test method for an optical chip in an integrated circuit. A captured image array is processed as a circle by: dividing the array into circular patterns on the basis of the radius, reconstructing the circular patterns into a two-dimensional array according to coordinates, and then performing corresponding operations on the obtained array to obtain a desired value. By the halo test method for an optical chip in an integrated circuit provided in the present invention, without increasing any extra hardware cost and under the primary test conditions, the technical problem in the prior art that there is no well-developed method and algorithm for testing halo on a fingerprint on display (FOD) chip is solved.Type: GrantFiled: June 14, 2019Date of Patent: April 13, 2021Assignee: Sino IC Technology Co., Ltd.Inventors: Hua Wang, Zhiyong Zhang, Weiwei Deng, Kun Yu, Haiying Ji, Bin Luo
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Publication number: 20200401022Abstract: The present disclosure relates to a stand. The stand may include a supporting component, a rotation component, a rotation limiting component, and an adapter ring. The rotation component may be rotatably connected to the supporting component and may be configured to rotate about a first rotation axis. The adapter ring may be placed between the rotation component and the rotation limiting component. The rotation component may include first ratchet teeth on a first side of the rotation component. The rotation limiting component may include second ratchet teeth on a second side of the rotation limiting component facing the first side. The adapter ring may include third ratchet teeth and fourth ratchet teeth on a third side and a fourth side of the adapter ring, respectively. The third ratchet teeth may be engaged with the first ratchet teeth and the fourth ratchet teeth may be engaged with the second ratchet teeth.Type: ApplicationFiled: September 2, 2020Publication date: December 24, 2020Applicant: ZHEJIANG DAHUA TECHNOLOGY CO., LTD.Inventors: Liang DONG, Zhengchun LUO, Zhiyong ZHANG
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Publication number: 20200384518Abstract: A manufacturing device for a bimetal composite hollow billet, includes a mandrel, a frame, a planetary carrier rotatably disposed on the frame, a plurality of rolls rotatably disposed on the planetary carrier, and disposed around the mandrel, and a bimetallic pipe to be processed is sleeved on the mandrel.Type: ApplicationFiled: April 30, 2020Publication date: December 10, 2020Applicant: Taiyuan PLS Technology Development Co., Ltd.Inventors: Zhiyong ZHANG, Kechuan WANG, Gaofeng SUN
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Publication number: 20200385281Abstract: Disclosed are basic copper chloride particulate matter and a preparation method therefor. The basic copper chloride particulate matter is mainly composed of basic copper chloride particles, and the basic copper chloride particles, with a particle size of 60-250 ?m, in the basic copper chloride particulate matter comprise 97% or more of the total mass of the basic copper chloride particulate matter.Type: ApplicationFiled: December 21, 2017Publication date: December 10, 2020Applicant: GUANGZHOU COSMO ENVIRONMENTAL TECHNOLOGY CO., LTD.Inventors: Zhiyuan HUANG, Yangdong WU, Zhiyong ZHANG, Hao WANG, Zhengjiong ZHA, Yongcheng WANG
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Publication number: 20200343353Abstract: A dual-gate transistor and its production method are disclosed. An auxiliary gate is connected to the power supply of the integrated circuits, to form thick and high square-shaped potential barrier of minority carriers adjacent to the drain electrode, while the potential barrier is transparent for the majority carriers from the source electrodes. The potential barrier can effectively inhibit reverse minority carrier tunneling from the drain electrode at large drain-source voltage. The transistor can be easily turned on at small drain-source voltage, without significantly decreasing the on-state current. The dual-gate transistor can significantly suppress ambipolar behavior with increased current on/off ratio and reduced power consumption, and maintain the high performance. Based on transistors, strengthened CMOS circuits can have high noise margin, low voltage loss, reduced logic errors, high performance and low power consumption.Type: ApplicationFiled: April 21, 2020Publication date: October 29, 2020Inventors: Chenyi Zhao, Donglai Zhong, Zhiyong Zhang, Lianmao Peng
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Patent number: 10794980Abstract: A method for MRI imaging of a subject includes spatially encoding spins in a slice of the subject in orthogonal first and second directions. The encoding includes applying a chirped radiofrequency (RF) pulse concurrently with application of a magnetic field gradient pulse along the first direction. After applying of the RF pulse, a second chirped RF pulse is applied concurrently with application of a second magnetic field gradient pulse, with polarity opposite that of the first gradient pulse. An encoding magnetic field gradient, constant from applying the first RF pulse until the end of applying the second RF pulse, is concurrently applied along the second direction. Following the encoding, a spin signal is measured concurrently with application of a constant readout magnetic field gradient.Type: GrantFiled: February 1, 2018Date of Patent: October 6, 2020Assignee: YEDA RESEARCH AND DEVELOPMENT CO. LTD.Inventors: Lucio Frydman, Zhiyong Zhang, Shimon Michael Lustig
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Publication number: 20200311375Abstract: The present invention discloses a halo test method for an optical chip in an integrated circuit. A captured image array is processed as a circle by: dividing the array into circular patterns on the basis of the radius, reconstructing the circular patterns into a two-dimensional array according to coordinates, and then performing corresponding operations on the obtained array to obtain a desired value. By the halo test method for an optical chip in an integrated circuit provided in the present invention, without increasing any extra hardware cost and under the primary test conditions, the technical problem in the prior art that there is no well-developed method and algorithm for testing halo on a fingerprint on display (FOD) chip is solved.Type: ApplicationFiled: June 14, 2019Publication date: October 1, 2020Inventors: Hua WANG, Zhiyong ZHANG, Weiwei DENG, Kun YU, Haiying JI, Bin LUO