Abstract: Tunable radio frequency (RF) devices, such as phase shifters and filters, are formed by depositing thin film layers on a substrate and patterning the thin film layers by various lithography techniques. A thin film metal layer is patterned to form a plurality of capacitors and inductors, leaving at least two grounding regions that lie closely adjacent the capacitors and inductors. As patterned portions of the grounding regions are electrically isolated from each other. Performance of the devices are improved by electrically bridging the differential potential grounding regions.

Abstract: Maternal diabetes can lead to a developmental malformation of an embryo. A developmental malformation caused by maternal diabetes is commonly referred to as a diabetic embryopathy. There is currently no effective treatment for reducing or inhibiting a diabetic embryopathy. To this end, the present invention is drawn to novel methods of treating a diabetic embryopathy.

Abstract: A method for manufacturing a bipolar transistor includes forming a first epitaxial layer on a semiconductor substrate, forming a second epitaxial layer on the first epitaxial layer, forming an oxide layer on the second epitaxial layer, etching the oxide layer to form an opening in which the second epitaxial layer is exposed, and forming a third epitaxial layer in the opening. The first and third epitaxial layers have a first-type conductivity, and the second epitaxial layer has a second-type conductivity.

Abstract: A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region,

Abstract: A method for manufacturing a bipolar transistor includes forming a first epitaxial layer on a semiconductor substrate, forming a second epitaxial layer on the first epitaxial layer, forming an oxide layer on the second epitaxial layer, etching the oxide layer to form an opening in which the second epitaxial layer is exposed, and forming a third epitaxial layer in the opening. The first and third epitaxial layers have a first-type conductivity, and the second epitaxial layer has a second-type conductivity.

Abstract: A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region,

Abstract: Maternal diabetes can lead to a developmental malformation of an embryo. A developmental malformation caused by maternal diabetes is commonly referred to as a diabetic embryopathy. There is currently no effective treatment for reducing or inhibiting a diabetic embryopathy. To this end, the present invention is drawn to novel methods of treating a diabetic embryopathy.

Abstract: Tunable radio frequency (RF) devices, such as phase shifters and filters, are formed by depositing thin film layers on a substrate and patterning the thin film layers by various lithography techniques. A thin film metal layer is patterned to form a plurality of capacitors and inductors, leaving at least two grounding regions that lie closely adjacent the capacitors and inductors. As patterned portions of the grounding regions are electrically isolated from each other. Performance of the devices are improved by electrically bridging the differential potential grounding regions.

Abstract: Disclosed herein are various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same. In one illustrative embodiment, the method includes providing a device substrate comprising a plurality of masked areas, a plurality of unmasked areas, and at least one doped region formed in the substrate, determining a ratio between the unmasked areas and the masked areas for the device substrate, illuminating an area of the device substrate comprising the masked areas, the unmasked areas, and at least one doped region, and measuring an induced surface photovoltage of the device substrate while accounting for the ratio of the unmasked areas and the masked areas of the device substrate.

Abstract: Electronic and optical (or photonic) devices with variable or switchable properties and methods used to form these devices, are disclosed. More specifically, the present invention involves forming layers of conductive material and dielectric material or materials with varying conductivity and indexes of refraction to form various electronic and optical devices. One such layer of adjustable material is formed by depositing epitaxial or reduced grain boundary barium strontium titanate on the C-plane of sapphire.

Abstract: Electronic and optical (or photonic) devices with variable or switchable properties and methods used to form these devices, are disclosed. More specifically, the present invention involves forming layers of conductive material and dielectric material or materials with varying conductivity and indexes of refraction to form various electronic and optical devices. One such layer of adjustable material is formed by depositing epitaxial or reduced grain boundary barium strontium titanate on the C-plane of sapphire.

Abstract: Electronic and optical (or photonic) devices with variable or switchable properties and methods used to form these devices, are disclosed. More specifically, the present invention involves forming layers of conductive material and dielectric material or materials with varying conductivity and indexes of refraction to form various electronic and optical devices. One such layer of adjustable material is formed by depositing epitaxial or reduced grain boundary barium strontium titanate on the C-plane of sapphire.

Abstract: Disclosed herein are various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same. In one illustrative embodiment, the method includes providing a device substrate comprising a plurality of masked areas, a plurality of unmasked areas, and at least one doped region formed in the substrate, determining a ratio between the unmasked areas and the masked areas for the device substrate, illuminating an area of the device substrate comprising the masked areas, the unmasked areas, and at least one doped region, and measuring an induced surface photovoltage of the device substrate while accounting for the ratio of the unmasked areas and the masked areas of the device substrate.

Abstract: A method for electrostatic discharge depolarization is implemented. The buildup of charge on tool structures in fabrication tools for semiconductor processing may be expected to be of concern whenever high voltage is employed near the structure in a tool. The process herein includes selectively exposing the structure to a plasma for a selected time interval. The duration of the exposure time interval is sufficient to reduce the polarization of the structure whereby the forces due to the polarization do not interfere with the transport or movement of a wafer being processed.

Abstract: A method is presented for compensating for the effects of charge neutralization in calculating the ‘true’ ion dose, i.e., the dose assuming no changes of charge state of ions during an implantation process. An ion beam is generated under normal operating conditions, e.g., stable vacuum exists, and no target is being implanted. At least one additional detector would be positioned in the target chamber, and a dose measurement conducted simultaneously with a measurement of the beam current with the Faraday, which is located outside of the charge neutralization region, to establish a reference ratio. A wafer is then placed at the target location, and simultaneous measurements made with the additional detector and Faraday, as before, to determine the ratio between the beam current and the detector during wafer implantation. Any drift from the reference ratio indicates the dose error due to charge neutralization from wafer outgassing during implantation.

Abstract: A Faraday system for measuring ion beam current in an ion implanter or other ion beam treatment system includes a Faraday cup body defining a chamber which has an entrance aperture for receiving an ion beam, a suppression electrode positioned in proximity to the entrance aperture to produce electric fields for inhibiting escape of electrons from the chamber, and a magnet assembly positioned to produce magnetic fields for inhibiting escape of electrons from the chamber. The chamber may have a relatively small ratio of chamber depth to entrance aperture width.

Abstract: Electronic and optical (or photonic) devices with variable or switchable properties and methods used to form these devices, are disclosed. More specifically, the present invention involves forming layers of conductive material and dielectric material or materials with varying conductivity and indexes of refraction to form various electronic and optical devices. One such layer of adjustable material is formed by depositing epitaxial or reduced grain boundary barium strontium titanate on the C-plane of sapphire.

Abstract: Various methods of determining ion implant dosage are disclosed. In one aspect, a method of processing a semiconductor workpiece that has a device region and an inactive region is provided. A first mask is formed on a first portion of the inactive region. A first implant of ions is performed on the device region and the first mask. A secondary ion mass spectrometry analysis of the first portion of the first mask is performed to determine a composition thereof relative to a standard composition. A dose for the first implant is determined based upon the secondary ion mass spectrometry analysis of the first portion of the first mask. The first implant dose is compared with a prescribed dose for the first implant to determine if a second implant is necessary to achieve the prescribed dose, and if so, an appropriate make-up dose for the second implant.

Abstract: An electrostatic lens with glassy graphite electrodes for use in an ion implanter is disclosed. The graphite electrodes have been manufactured to be substantially smooth (glassy) such that irregularities on the surface grain of the graphite, for example peaks or apexes, are no longer present. In an embodiment, employing polished graphite electrostatic lens electrodes does not require the time-consuming conditioning operations under vacuum that are typically needed with conventional graphite electrodes, and thus offers the advantage of increased uptime for an ion implantation system. In addition, because surface irregularities are not present to serve as discharge points for electrostatic buildup, the use of glassy graphite electrodes as disclosed offers the advantage of electrostatic discharge reduction.

Abstract: A Faraday system for measuring ion beam current in an ion implanter or other ion beam treatment system includes a Faraday cup body defining a chamber which has an entrance aperture for receiving an ion beam, a suppression electrode positioned in proximity to the entrance aperture to produce electric fields for inhibiting escape of electrons from the chamber, and a magnet assembly positioned to produce magnetic fields for inhibiting escape of electrons from the chamber. The chamber may have a relatively small ratio of chamber depth to entrance aperture width.