Patents by Inventor Zhiyu Ru
Zhiyu Ru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10931288Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.Type: GrantFiled: December 26, 2019Date of Patent: February 23, 2021Assignee: Avago Technologies International Sales Pte. LimitedInventors: Zhiyu Ru, Tim Yee He, Siavash Fallahi, Ali Nazemi, Delong Cui, Jun Cao
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Publication number: 20200304129Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.Type: ApplicationFiled: December 26, 2019Publication date: September 24, 2020Inventors: Zhiyu RU, Tim Yee HE, Siavash FALLAHI, Ali NAZEMI, Delong CUI, Jun CAO
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Patent number: 10623044Abstract: An apparatus for phase and frequency detection (PFD) includes a first circuit to receive a first input pulse and to generate a first output pulse, the rising edge of which is triggered by a first rising edge of the first input pulse, and a second circuit coupled to the first circuit and configured to receive a second input pulse and to generate a second output pulse, the rising edge of which is triggered by a second rising edge of the second input pulse. The second output pulse has a falling edge carrying first information related to a first rising edge of the first input pulse. The first output pulse has a falling edge carrying second information related to a second rising edge of the second input pulse.Type: GrantFiled: August 20, 2018Date of Patent: April 14, 2020Assignee: Avago Technologies International Sales Pte. LimitedInventors: Zhiyu Ru, Jun Cao
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Publication number: 20200059260Abstract: An apparatus for phase and frequency detection (PFD) includes a first circuit to receive a first input pulse and to generate a first output pulse, the rising edge of which is triggered by a first rising edge of the first input pulse, and a second circuit coupled to the first circuit and configured to receive a second input pulse and to generate a second output pulse, the rising edge of which is triggered by a second rising edge of the second input pulse. The second output pulse has a falling edge carrying first information related to a first rising edge of the first input pulse. The first output pulse has a falling edge carrying second information related to a second rising edge of the second input pulse.Type: ApplicationFiled: August 20, 2018Publication date: February 20, 2020Inventors: Zhiyu RU, Jun CAO
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Patent number: 10523220Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.Type: GrantFiled: March 18, 2019Date of Patent: December 31, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventors: Zhiyu Ru, Tim Yee He, Siavash Fallahi, Ali Nazemi, Delong Cui, Jun Cao
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Patent number: 8606210Abstract: A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.Type: GrantFiled: February 3, 2010Date of Patent: December 10, 2013Assignee: NXP, B.V.Inventors: Zhiyu Ru, Eric A. M. Klumperink, Bram Nauta, Johannes H. A. Brekelmans
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Publication number: 20110298521Abstract: A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.Type: ApplicationFiled: February 3, 2010Publication date: December 8, 2011Applicant: NXP B.V.Inventors: Zhiyu Ru, Eric A. M. Klumperink, Bram Nauta, Johannes H. A. Brekelmans