Patents by Inventor Zhiyu Zhao

Zhiyu Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11688178
    Abstract: The embodiments of the present disclosure provide a system for calculating a regional crowd movement and a method thereof. The system is applied to a target monitoring environment, a plurality of key travel nodes are planned in the target monitoring environment, and the system includes radio frequency labels deployed on pedestrians, calculation apparatuses deployed at the key travel nodes and a plurality of directional antennas. The directional antenna is configured to, when driven by the calculation apparatus, send a read-write signal to the radio frequency label in a coverage region; the directional antenna is further configured to forward a radio frequency signal simultaneously reflected by the radio frequency label at the time of obtaining the read-write signal to the calculation apparatus; the calculation apparatus is configured to, based on a tempo-spatial distribution circumstance of the radio frequency signals in the region.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: June 27, 2023
    Assignees: China Construction First Group Corporation Limited, China Construction First group Huabei Construction Co., Ltd., Lanjian (Suzhou) Technology Co., Ltd
    Inventors: Lei Chen, Wei Xu, Zhiyu Zhao, Ruoxuan Mei, Weiyu Su, Ziqi Zhou, Zhengang Zhao, Yuze Wang, Yanting He, Xiaojiao Xiao, Guoxu Zhang, Jing Tong, Le Wang, Ling Wang, Zijin Liao
  • Patent number: 10430364
    Abstract: When a first interface board receives from an Ethernet switch chip a first Ethernet data packet, once a destination board of the data packet is determined as second interface board logical device of the first interface board encapsulates the data packet into a PCI-E packet that takes a PCI-E memory space address of a board memory in the second interface board as a destination address, so as to enable a PCI-E Endpoint to forward the first PCI-E packet to a forwarding board of a network device; when the first interface board obtains from a board memory a second PCI-E packet coming from a third interface board, logical device of the first interface board parses out a Ethernet data packet from the second PCI-E packet, and transmits the data packet to the Ethernet switch chip, the third interface board and second interface board being the same or not same.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 1, 2019
    Assignee: New H3C Technologies Co., Ltd.
    Inventors: Zhiyu Zhao, Changlin Mu, Yanfeng Zuo
  • Patent number: 10432557
    Abstract: A network device may include a first forwarding board, a second forwarding board and an interface board. The interface board may include a control apparatus and a network interface chip. The control apparatus may form a first upstream packet flow which is sent to the first forwarding board via a first I/O bus and a second upstream packet flow which is sent to the second forwarding board via a second I/O bus using data packets received through the network interface chip from the exterior of the network device.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 1, 2019
    Assignee: NEW H3C TECHNOLOGIES CO., LTD
    Inventor: Zhiyu Zhao
  • Patent number: 10419355
    Abstract: In an example, a logic apparatus of an interface board in a network device may generate an Ethernet flow control packet including sending completion information according to Ethernet data packets sent from a sending buffering queue maintained in the interface board. The logic apparatus of the interface board may transmit the Ethernet flow control packet including sending completion information to an Ethernet data channel by taking priority over Ethernet data packets in a receiving buffering queue in an ingress direction. The sending completion information is used by a CPU of a mainboard to maintain a state of the sending buffering queue.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 17, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Zhiyu Zhao, Ze Zhang, Changlin Mu
  • Publication number: 20180241698
    Abstract: A network device may include a first forwarding board, a second forwarding board and an interface board. The interface board may include a control apparatus and a network interface chip. The control apparatus may form a first upstream packet flow which is sent to the first forwarding board via a first I/O bus and a second upstream packet flow which is sent to the second forwarding board via a second I/O bus using data packets received through the network interface chip from the exterior of the network device.
    Type: Application
    Filed: August 25, 2016
    Publication date: August 23, 2018
    Inventor: Zhiyu ZHAO
  • Publication number: 20180225247
    Abstract: When a first interface board receives from an Ethernet switch chip a first Ethernet data packet, once a destination board of the data packet is determined as second interface board logical device of the first interface board encapsulates the data packet into a PCI-E packet that takes a PCI-E memory space address of a board memory in the second interface board as a destination address, so as to enable a PCI-E Endpoint to forward the first PCI-E packet to a forwarding board of a network device; when the first interface board obtains from a board memory a second PCI-E packet coming from a third interface board, logical device of the first interface board parses out a Ethernet data packet from the second PCI-E packet, and transmits the data packet to the Ethernet switch chip, the third interface board and second interface board being the same or not same.
    Type: Application
    Filed: October 31, 2016
    Publication date: August 9, 2018
    Inventors: Zhiyu ZHAO, Changlin MU, Yanfeng ZUO
  • Publication number: 20180048582
    Abstract: In an example, a logic apparatus of an interface board in a network device may generate an Ethernet flow control packet including sending completion information according to Ethernet data packets sent from a sending buffering queue maintained in the interface board. The logic apparatus of the interface board may transmit the Ethernet flow control packet including sending completion information to an Ethernet data channel by taking priority over Ethernet data packets in a receiving buffering queue in an ingress direction. The sending completion information is used by a CPU of a mainboard to maintain a state of the sending buffering queue.
    Type: Application
    Filed: February 5, 2016
    Publication date: February 15, 2018
    Inventors: Zhiyu Zhao, Ze Zhang, Changlin Mu