Patents by Inventor Zhi-Yuan Cheng

Zhi-Yuan Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7626246
    Abstract: Methods of forming areas of alternative material on crystalline semiconductor substrates, and structures formed thereby. Such areas of alternative material are suitable for use as active areas in MOSFETs or other electronic or opto-electronic devices.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: December 1, 2009
    Assignee: Amberwave Systems Corporation
    Inventors: Anthony J. Lochtefeld, Matthew T. Currie, Zhi-Yuan Cheng, James Fiorenza
  • Publication number: 20070181977
    Abstract: Methods of forming areas of alternative material on crystalline semiconductor substrates, and structures formed thereby. Such areas of alternative material are suitable for use as active areas in MOSFETs or other electronic or opto-electronic devices.
    Type: Application
    Filed: July 26, 2006
    Publication date: August 9, 2007
    Applicant: AmberWave Systems Corporation
    Inventors: Anthony Lochtefeld, Matthew Currie, Zhi-Yuan Cheng, James Fiorenza
  • Patent number: 6921914
    Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1-yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1-xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth.
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: July 26, 2005
    Assignee: Massachusetts Institute of Technology
    Inventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
  • Publication number: 20050009288
    Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1-yGey layer remains on the second substrate. In another exemplary embodiment, a graded SixGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth.
    Type: Application
    Filed: March 17, 2004
    Publication date: January 13, 2005
    Applicant: Massachusetts Institute of Technology
    Inventors: Zhi-Yuan Cheng, Eugene Fitzgerald, Dimitri Antoniadis, Judy Hoyt
  • Publication number: 20040173791
    Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1-yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1-xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth.
    Type: Application
    Filed: March 17, 2004
    Publication date: September 9, 2004
    Applicant: Massachusetts Institute of Technology
    Inventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
  • Patent number: 6737670
    Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: May 18, 2004
    Assignee: Massachusetts Institute of Technology
    Inventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
  • Patent number: 6713326
    Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: March 30, 2004
    Assignee: Masachusetts Institute of Technology
    Inventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
  • Publication number: 20030168654
    Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.
    Type: Application
    Filed: March 7, 2003
    Publication date: September 11, 2003
    Applicant: Massachusetts Institute of Technology
    Inventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
  • Publication number: 20030155568
    Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.
    Type: Application
    Filed: March 4, 2003
    Publication date: August 21, 2003
    Applicant: Massachusetts Institute of Technology
    Inventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
  • Patent number: 6573126
    Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: June 3, 2003
    Assignee: Massachusetts Institute of Technology
    Inventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
  • Publication number: 20020072130
    Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydrogen ions are then introduced into the strained SizGz layer. The relaxed Si1-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1-yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1-xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth.
    Type: Application
    Filed: August 10, 2001
    Publication date: June 13, 2002
    Inventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt