Patents by Inventor Zhiyuan LENG

Zhiyuan LENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system of reducing address mapping space of flash translation layer
    Patent number: 11429533
    Abstract: A method of reducing FTL address mapping space, including: S1, obtaining a mpa and an offset according to a logical page address; S2, determining whether the mpa is hit in a cache; S3, determining whether a NAND is written into the mpa; S4, performing a nomap load operation, and returning an invalid mapping; S5, performing a map load operation; S6, directly searching a mpci representing a position of the mpa in the cache and searching a physical page address gppa with reference to the offset; S7, determining whether a mapping from a logical address to a physical address needs to be modified; S8, modifying a mapping table corresponding to the mpci in the cache, and marking a mp corresponding to the mpci as a dirty mp; S9, determining whether to trigger a condition of writing the mp into the NAND; and S10, writing the dirty mp into the NAND.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 30, 2022
    Assignee: SHENZHEN UNIONMEMORY INFORMATION SYSTEM LIMITED
    Inventors: Jian Zuo, Yuanyuan Feng, Zhiyuan Leng, Jintao Gan, Weiliang Wang, Zongming Jia
  • METHOD AND SYSTEM OF REDUCING FTL ADDRESS MAPPING SPACE
    Publication number: 20210019265
    Abstract: A method of reducing FTL address mapping space, including: S1, obtaining a mpa and an offset according to a logical page address; S2, determining whether the mpa is hit in a cache; S3, determining whether a NAND is written into the mpa; S4, performing a nomap load operation, and returning an invalid mapping; S5, performing a map load operation; S6, directly searching a mpci representing a position of the mpa in the cache and searching a physical page address gppa with reference to the offset; S7, determining whether a mapping from a logical address to a physical address needs to be modified; S8, modifying a mapping table corresponding to the mpci in the cache, and marking a mp corresponding to the mpci as a dirty mp; S9, determining whether to trigger a condition of writing the mp into the NAND; and S10, writing the dirty mp into the NAND.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 21, 2021
    Inventors: Jian ZUO, Yuanyuan FENG, Zhiyuan LENG, Jintao GAN, Weiliang WANG, Zongming JIA