Abstract: This application provides a game login method. The game login method includes receiving a login request sent by a client computing device, where the login request carries a login account; determining at least two groups of corresponding network addresses based on the login account; determining whether the client computing device belongs to a lock region based on lock region configuration corresponding to the login request and the at least two groups of network addresses; and in response to determining that the client computing device does not belong to the lock region, performing login based on the login request.

Abstract: This invention discloses a semiconductor power device formed on a semiconductor substrate comprises an active cell area and a termination area disposed near edges of the semiconductor substrate. The termination area comprises a plurality of duplicated units wherein each unit includes at least two trenches filled with a conductive trench material having a mesa area between adjacent trenches wherein the trenches and the mesa areas within each of the duplicated units are electrically shunt together. In the termination area each of the trenches in the duplicated units has a buried guard ring dopant region disposed below a bottom surface of the trenches.

Abstract: A semiconductor power device includes a plurality of power transistor cells each having a trenched gate disposed in a gate trench opened in a semiconductor substrate wherein a plurality of the trenched gates further include a shielded bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed at a top portion of the gate trench by an inter-electrode insulation layer. At least one of the shielded bottom electrode is connected a source metal and at least one of the top electrodes in the gate trench is connected to a source metal of the power device.

Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

Abstract: This invention discloses a semiconductor power device formed on a semiconductor substrate comprises an active cell area and a termination area disposed near edges of the semiconductor substrate. The termination area comprises a plurality of duplicated units wherein each unit includes at least two trenches filled with a conductive trench material having a mesa area between adjacent trenches wherein the trenches and the mesa areas within each of the duplicated units are electrically shunt together. In the termination area each of the trenches in the duplicated units has a buried guard ring dopant region disposed below a bottom surface of the trenches.

Abstract: A semiconductor power device includes a plurality of power transistor cells each having a trenched gate disposed in a gate trench opened in a semiconductor substrate wherein a plurality of the trenched gates further include a shielded bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed at a top portion of the gate trench by an inter-electrode insulation layer. At least one of the shielded bottom electrode is connected a source metal and at least one of the top electrodes in the gate trench is connected to a source metal of the power device.

Abstract: A semiconductor power device includes a plurality of power transistor cells each having a trenched gate disposed in a gate trench opened in a semiconductor substrate wherein a plurality of the trenched gates further include a shielded bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed at a top portion of the gate trench by an inter-electrode insulation layer. At least one of the shielded bottom electrode is connected a source metal and at least one of the top electrodes in the gate trench is connected to a source metal of the power device.

Abstract: A semiconductor power device includes a plurality of power transistor cells each having a trenched gate disposed in a gate trench opened in a semiconductor substrate wherein a plurality of the trenched gates further include a shielded bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed at a top portion of the gate trench by an inter-electrode insulation layer. At least one of the shielded bottom electrode is connected a source metal and at least one of the top electrodes in the gate trench is connected to a source metal of the power device.

Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.