Patents by Inventor Zhong Chen

Zhong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240329361
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.
    Type: Application
    Filed: June 7, 2024
    Publication date: October 3, 2024
    Inventors: Sin-Hong LIN, Yung-Ping YANG, Wen-Yen HUANG, Yu-Cheng LIN, Kun-Shih LIN, Chao-Chang HU, Yung-Hsien YEH, Mao-Kuo HSU, Chih-Wei WENG, Ching-Chieh HUANG, Chih-Shiang WU, Chun-Chia LIAO, Chia-Yu CHANG, Hung-Ping CHEN, Wei-Zhong LUO, Wen-Chang LIN, Shou-Jen LIU, Shao-Chung CHANG, Chen-Hsin HUANG, Meng-Ting LIN, Yen-Cheng CHEN, I-Mei HUANG, Yun-Fei WANG, Wei-Jhe SHEN
  • Publication number: 20240332174
    Abstract: An IC device includes first and second circuits adjacent each other and over a substrate. The first circuit includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second circuit includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second circuit or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connecting the first IO pattern and a second IO pattern of the second circuit. The second IO pattern is one of the plurality of conductive patterns of the second circuit and is along the first track.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Inventors: Cheng-Yu LIN, Jung-Chan YANG, Hui-Zhong ZHUANG, Sheng-Hsiung CHEN, Kuo-Nan YANG, Chih-Liang CHEN, Lee-Chung LU
  • Patent number: 12108593
    Abstract: A method includes the following operations for preparing a semiconductor structure, a semiconductor, and a semiconductor memory. A first dielectric layer and a first barrier layer are deposited on a substrate including an active area in sequence. A first mask including a first etching pattern is formed on the first barrier layer, and includes a groove extending in a first direction and uniformly distributed etching holes. Herein, the groove penetrates through the etching hole, and the depth of the etching hole is larger than that of the groove. Etching is performed along the first etching pattern, to remove the first barrier layer and etch the first dielectric layer to form a conductive channel.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: October 1, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yexiao Yu, Longyang Chen, Zhongming Liu, Zhong Kong
  • Publication number: 20240321870
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first gate structure on a first side of the substrate. The semiconductor device further includes a second gate structure on a second side of the substrate, wherein the first side is opposite the second side. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.
    Type: Application
    Filed: June 5, 2024
    Publication date: September 26, 2024
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
  • Publication number: 20240317504
    Abstract: This application provides a load-bearing support plate, chain structure, and a conveyor belt structure incorporating them, the load-bearing support plate comprises a first panel, a second panel, and a transition panel for connecting the first panel with the second panel; the first panel is offset in a first direction relative to the second panel, at least one reinforcing rib provided on the first panel, the reinforcing rib extending upwards from the bottom of the first panel to the upper edge of the first panel and forming a bearing surface with the top surface of the first panel. By forming the first panel into a curved shape with the use of reinforcing ribs, the overall support capability is enhanced. Also, by extending the reinforcing ribs to the upper edge of the first panel, the upper edge of the support plate below becomes curved, offering a larger contact area in the thickness direction, thereby improving the stability of the spiral stacking motion.
    Type: Application
    Filed: March 18, 2024
    Publication date: September 26, 2024
    Applicant: Square Technology Group Co., Ltd
    Inventors: Xiaoyan YANG, Xiaohua LOU, Pu CHEN, Zhong PU, Wenbo AI, Yafei SHAN
  • Publication number: 20240311185
    Abstract: Methods and apparatus consistent with the present disclosure may be used in environments where multiple different virtual sets of program instructions are executed by shared computing resources. These methods may allow actions associated with a first set of virtual software to be paused to allow a second set of virtual software to be executed by the shared computing resources. In certain instances, methods and apparatus consistent with the present disclosure may manage the operation of one or more sets of virtual software at a point in time. Apparatus consistent with the present disclosure may include a memory and one or more processors that execute instructions out of the memory. At certain points in time, a processors of a computing system may pause a virtual process while allowing instructions associated with another virtual process to be executed.
    Type: Application
    Filed: April 2, 2024
    Publication date: September 19, 2024
    Inventors: Miao Mao, Wei Zhou, Zhong Chen
  • Patent number: 12095779
    Abstract: The present disclosure relates to a system, a method, and a non-transitory computer readable storage medium for deep packet inspection scanning at an application layer of a computer. A method of the presently claimed invention may scan pieces of data received out of order without reassembly at an application layer from a first input state generating one or more output states for each piece of data. The method may then identify that the first input state includes one or more characters that are associated with malicious content. The method may then identify that the data set may include malicious content when the first input state combined with one or more output states matches a known piece of malicious content.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: September 17, 2024
    Assignee: SonicWALL Inc.
    Inventors: Hui Ling, Cuiping Yu, Zhong Chen
  • Publication number: 20240297067
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Application
    Filed: May 15, 2024
    Publication date: September 5, 2024
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Publication number: 20240288984
    Abstract: The embodiment of the invention discloses an interaction method, device and equipment, and a storage medium. A first user triggers an object adding operation aiming at a first object in a session interface for performing a conversation with one or more second users, then a client adds the first object in the session interface according to the object adding operation, the first object can be accessed by one or more second users, that is to say, after the first object is added in the session interface, the first user or the second user can directly and quickly access the first object on the session interface, the first object can be found without a chat record, and convenience is brought to the users.
    Type: Application
    Filed: August 12, 2022
    Publication date: August 29, 2024
    Inventors: Fangjia CHEN, Yonghao ZHANG, Zhong WANG, Qianmin ZHANG
  • Patent number: 12074168
    Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Guo-Huei Wu, Jerry Chang Jui Kao, Chih-Liang Chen, Hui-Zhong Zhuang, Jung-Chan Yang, Lee-Chung Lu, Xiangdong Chen
  • Publication number: 20240279418
    Abstract: A thermoplastic polyurethane foam material, a midsole of athletic shoe and a manufacturing method of a foam material are provided. The thermoplastic polyurethane foam material includes a diphenylmethane diisocyanate, a polytetramethylene ether glycol, a 1,4-butanediol, a nucleating agent and a thinning agent. The thinning agent has a structure represented by formula (I), of which each symbol is defined in the specification.
    Type: Application
    Filed: January 31, 2024
    Publication date: August 22, 2024
    Inventors: Shih-Wei LIU, Jing-Zhong HWANG, Pin-Jung CHEN, Chang-Yen CHANG, Shih-Chieh WU
  • Publication number: 20240274607
    Abstract: A method includes fabricating a first-voltage underlayer power rail conductively connecting to the source region of a first-type transistor and fabricating a second-voltage underlayer power rail conductively connecting to the source region of a second-type transistor. Each of the first-voltage and second-voltage underlayer power rails extends in a first direction. The method also includes patterning a first connection layer to form a first-voltage power rail and a second-voltage power rail extending in the second direction which is perpendicular to the first direction. The first-voltage power rail is directly connected with the first-voltage underlayer power rail through a first via-connector and the second-voltage power rail is directly connected with the second-voltage underlayer power rail through a second via-connector.
    Type: Application
    Filed: April 22, 2024
    Publication date: August 15, 2024
    Inventors: Guo-Huei WU, Shih-Wei PENG, Wei-Cheng LIN, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN, Lee-Chung LU
  • Publication number: 20240274125
    Abstract: According to one embodiment, a method, computer system, and computer program product for building an acoustic model is provided. The present invention may include performing contrastive pre-training of the acoustic model; building a dataset classifier using prompt engineering; performing a prediction process; and performing zero-shot audio prediction using the pre-trained acoustic model.
    Type: Application
    Filed: February 10, 2023
    Publication date: August 15, 2024
    Inventors: Zhong Fang Yuan, Si Tong Zhao, Tong Liu, Yi Chen Zhong, Yuan Yuan Ding
  • Patent number: 12063780
    Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: August 13, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Xiaowang Dai, Zhenyu Lu, Jun Chen, Qian Tao, Yushi Hu, Jifeng Zhu, Jin Wen Dong, Ji Xia, Zhong Zhang, Yan Ni Li
  • Patent number: 12062570
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: August 13, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Patent number: 12060505
    Abstract: Provided are double-coated tapes that include, in the following order: a first pressure-sensitive adhesive layer; a first plastic skin layer; an elastic base layer; a second plastic skin layer; and a second pressure-sensitive adhesive layer. The provided double-coated adhesive tapes can provide a combination of high bond strength, reworkability, and high impact and shock resistance, and can be easily converted using a die cutting process.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: August 13, 2024
    Assignee: 3M Innovative Properties Company
    Inventors: Jingjing Ma, You-Hoon Kim, Christopher J. Rother, Gregory L. Bluem, Zhong Chen, Sarang V. Deodhar, Peter J. Klopp
  • Publication number: 20240265719
    Abstract: Embodiments of the present disclosure provide systems and methods for implementing enhanced Optical Character Recognition (OCR) of text overlapping scenes through text graph structuring. Text graph structuring is performed to provide a graph data structure for each data character or letter of multiple letters and a library of graph templates from graph structured data of each of the multiple letters. Text graph structuring is performed to convert visual content of an identified overlapping text image region to an overlapping text topology graph. The overlapping text topology graph is split into multiple subgraphs using the graph template library to match recognizable letters in the overlapping text.
    Type: Application
    Filed: February 6, 2023
    Publication date: August 8, 2024
    Inventors: Yuan Yuan DING, Zhong Fang YUAN, Tong LIU, Si Tong ZHAO, Yi Chen ZHONG
  • Publication number: 20240256750
    Abstract: A semiconductor device includes: single-bit flip-flop regions (SBFF regions) which comprise a multi-bit flip-flop (MBFF) region; the MBFF region having a two-dimensional floor plan represented by a grid including rows and a first column extending in corresponding first and perpendicular second directions, each SBFF region representing an intersection of a corresponding row and column; the SBFF regions being coupled in a daisy chain for which an output of a preceding one of the SBFF regions in the daisy chain is coupled to an input of a succeeding one of the SBFF regions in the daisy chain; and orientations of the SBFF regions relative to the first direction (?-orientations) being arranged in an alternating pattern relative to the second direction so that a two-dimensional representation of a flow path of a data signal along the first column has a serpentine shape.
    Type: Application
    Filed: January 27, 2023
    Publication date: August 1, 2024
    Inventors: Chih-Cheng CHUANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Wei-Hsiang MA
  • Publication number: 20240257815
    Abstract: The disclosure herein describes using a transcript generation model for generating a transcript from a multi-speaker audio stream. Audio data including overlapping speech of a plurality of speakers is obtained and a set of frame embeddings are generated from audio data frames of obtained audio data using an audio data encoder. A set of words and channel change (CC) symbols are generated from the set of frame embeddings using a transcript generation model. The CC symbols are included between pairs of adjacent words that are spoken by different people at the same time. The set of words and CC symbols are transformed into a plurality of transcript lines, wherein words of the set of words are sorted into transcript lines based on CC symbols, and a multi-speaker transcript is generated based on the plurality of transcript lines. The inclusion of CC symbols by the model enables efficient, accurate multi-speaker transcription.
    Type: Application
    Filed: April 10, 2024
    Publication date: August 1, 2024
    Inventors: Naoyuki KANDA, Takuya YOSHIOKA, Zhuo CHEN, Jinyu LI, Yashesh GAUR, Zhong MENG, Xiaofei WANG, Xiong XIAO
  • Publication number: 20240243065
    Abstract: A device includes: at a front side of a substrate, a first conductive line; and at a back side of the substrate, first to fifth power rails in a same back side metal layer; and wherein, within a span of a first cell, the second power rail is between the third and fourth power rails; each of the first to fifth power rails is configured different reference voltages first to third reference voltages, the first conductive line is configured to receive a control signal, an input signal, an output signal or one of the reference voltages; and relative to a center of the second power rail, a distribution of the first, second and third reference voltages amongst the first to fifth power rails is (A) symmetric with respect to a first direction and (B) symmetric with respect to perpendicular second direction.
    Type: Application
    Filed: April 1, 2024
    Publication date: July 18, 2024
    Inventors: Guo-Huei WU, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN