Patents by Inventor Zhong Chen

Zhong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210059762
    Abstract: A method and a system for registering real-time intra-operative image data of a body to a model of the body, the method comprising, segmenting a plurality of image data of the body obtained using a pre-operative imaging device; constructing the model of the body from the segmented plurality of image data; identifying one or more landmark features on the model of the body; acquiring the real-time intra-operative image data of the body using an intra-operative imaging device; and registering the real-time intra-operative image data of the body to the model of the body by matching one or more landmark features labelled on the real-time intra-operative image data to one or more corresponding landmark features on the model of the body, wherein the one or more landmark features comprises a superior and an inferior pole of the body.
    Type: Application
    Filed: December 28, 2018
    Publication date: March 4, 2021
    Inventors: Foo Cheong NG, Sey Kiat Terence LIM, Subburaj KARUPPPASAMY, U-Xuan TAN, Lujie CHEN, Shaohui FOONG, Liangjing YANG, Hsieh-Yu LI, Ishara Chaminda Kariyawasam PARANAWITHANA, Zhong Hoo CHAU, Muthu Rama Krishnan MOOKIAH
  • Publication number: 20210061581
    Abstract: A self-adaptive luggage transfer device and system. The self-adaptive luggage transfer device includes a base, a conveyor mechanism, a lifting mechanism and a self-adaptive extendable transfer mechanism. The lifting mechanism is arranged between the conveyor mechanism and the base and is configured to drive the conveyor mechanism to lift. The self-adaptive extendable transfer mechanism is obliquely arranged between the conveyor mechanism and the base and is in transmission connection with the lifting mechanism. Two ends of the self-adaptive extendable transfer mechanism are movably connected to an output end of the conveyor mechanism and the base, respectively. The conveyor mechanism is configured to drive an end of the self-adaptive extendable transfer mechanism connected to the conveyor mechanism to lift in a first direction, and the lifting mechanism is configured to drive at least one end of the self-adaptive extendable transfer mechanism to move in a second direction.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 4, 2021
    Inventors: Wenqiang LI, Song LI, Chen CHEN, Zhong TANG, Wu ZHAO, Chuanxiao LI
  • Publication number: 20210056498
    Abstract: The present disclosure provides a method and device for identifying a product purchased by a user and intelligent shelf system. The method includes acquiring a weight of products carried in a container, acquiring a first monitoring image acquired in a monitoring area corresponding to the container, identifying the first monitoring image, and obtaining an identification result, wherein the identification result comprises user identity information when it is determined that the weight of the products is reduced, acquiring a time when at least one product carried in the container is picked up, and determining information of at least one picked-up product, obtaining the user identity information corresponding to the at least one picked-up product, and associating the user identity information with the information of the at least one picked-up product.
    Type: Application
    Filed: February 14, 2019
    Publication date: February 25, 2021
    Applicants: BEIJING JINGDONG SHANGKE INFORMATION TECHNOLOGY CO., LTD., BEIJING JINGDONG CENTURY TRADING CO., LTD.
    Inventors: Wei LIU, Yu CHEN, Qiang LIU, Zhi WENG, Yi Jun FENG, Zhong Yu ZHANG
  • Publication number: 20210041588
    Abstract: The present disclosure discloses a method for identifying a boundary of a sedimentary facies, a computer device and a computer readable storage medium. The method comprises: acquiring a preliminary marked result of the sedimentary facies in a seismic attribute map; acquiring a color-based K-means classification result of the seismic attribute map by using a maximal between-cluster variance and a K-means clustering; acquiring a super-pixel classification result of the seismic attribute map according to a SLIC super-pixel segmentation; and performing a region growing fusion on the super-pixel classification result by taking the preliminary marked result and the K-means classification result as constraints, to determine an identification result of the boundary of the sedimentary facies in the seismic attribute map.
    Type: Application
    Filed: August 7, 2020
    Publication date: February 11, 2021
    Inventors: Qilin CHEN, Xingmiao YAO, Changkuan NI, Bo YAN, Huaqing LIU, Guangmin HU, Zhong HONG, Haichao JIAO
  • Publication number: 20210036707
    Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Jaeduk Han, Wenbo Liu, Wing Liu, Ming-Shuan Chen, Sanjeev K. Maheshwari, Vishal Varma, Sunil Bhosekar, Lizhi Zhong, Gary A. Rogan
  • Publication number: 20210010356
    Abstract: The disclosure provides a gasflow distribution device, a gas distributor, a pipe string and a method for separate-layer gas injection. The device includes an outer pipe, a gland, a filter screen, and a filling block with a pore structure; the outer pipe is a hollow outer pipe, used for containing the filling block, with an open upper end and a lower end with a bottom of which the center part is provided with a bottom hole, wherein the filling block is sealed to the inner wall of the outer pipe; the gland has a bottom end provided with a circular groove for setting the filter screen, and a top end distributed evenly with a plurality of top holes through the gland; and the gland is connected to the outer pipe, and the filter screen is pressed tightly against the filling block after the gland is connected to the outer pipe.
    Type: Application
    Filed: April 15, 2020
    Publication date: January 14, 2021
    Applicant: PETROCHINA COMPANY LIMITED
    Inventors: Xinglong CHEN, Jingyao WANG, Chengming ZHANG, Shitou WANG, Jiazhong WU, Zhong REN
  • Publication number: 20210005634
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 7, 2021
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Publication number: 20210004335
    Abstract: A method for automatically configuring a PCIe slot comprises: writing a configuration value into a storage device, with the configuration value associated with a configuration manner of the PCIE slot, reading the configuration value from the storage device by a BIOS, and determining whether the configuration value belongs to a valid value set, the BIOS configures a data bandwidth of the PCIe slot according to the configuration value when the configuration value belongs to a valid value set, and the BIOS configures the data bandwidth of the PCIe slot according to a default value when the configuration values does not belong to the valid value set.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 7, 2021
    Inventors: Jin CHEN, Zhong-Ying QU
  • Publication number: 20210005625
    Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiaowang DAI, Zhenyu LU, Jun CHEN, Qian TAO, Yushi HU, Jifeng ZHU, Jin Wen DONG, Ji XIA, Zhong ZHANG, Yan Ni LI
  • Publication number: 20210005633
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 7, 2021
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Patent number: 10879229
    Abstract: A method of forming an integrated circuit structure includes placing a tap cell layout pattern on a layout level, placing a set of standard cell layout patterns adjacent to the tap cell layout pattern, and manufacturing the integrated circuit structure based on at least one of the layout patterns. The placing the first well layout pattern includes placing a first layout pattern extending in a first direction and having a first width, placing a second layout pattern adjacent to the first layout pattern, and having a second width greater than the first width, and placing a first implant layout pattern on a second layout level, extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Yi-Hsun Chiu
  • Publication number: 20200402968
    Abstract: A semiconductor device includes first cell rows and second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. The second cell rows extend in the first direction. Each of the second cell rows has a second row height. The first row height is greater than the second row height. The first cell rows and the second cell rows are interlaced in a periodic sequence. A first row quantity of the first cell rows in the periodic sequence is greater than a second row quantity of the second cell rows in the periodic sequence.
    Type: Application
    Filed: April 22, 2020
    Publication date: December 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-Zhong ZHUANG, Xiang-Dong CHEN, Lee-Chung LU, Tzu-Ying LIN, Yung-Chin HOU
  • Patent number: 10871969
    Abstract: A method for switching basic input/output system (BIOS) interface, adapted to a basic input/output system (BIOS) having a complex module and a simplified module and executed by an electronic device, comprising entering a BIOS and displaying the simplified module on the BIOS interface, determining by the electronic device whether a hotkey is triggered, determining by the electronic device whether the hotkey is a first hotkey corresponding to the complex module when the hotkey is triggered, and hiding the simplified module and displaying the complex module on the BIOS interface when the hotkey is the first hotkey.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: December 22, 2020
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Jin Chen, Lai Kong, Zhong-Ying Qu
  • Patent number: 10871280
    Abstract: A connection terminal is provided, including at least one impedance branch circuit, where each impedance branch circuit includes one or more impedance elements and two first conductive connectors, each first conductive connector has a first end and a second end, first ends of the two first conductive connectors are configured to be coupled with a driving power supply and an illumination lamp, and second ends of the two first conductive connectors are configured to be coupled with two ends of the one or more impedance elements. An illumination device is provided, including a driving power supply, an illumination lamp and the connection terminal in the present disclosure, input ends of the driving power supply are coupled with an AC power grid, its out ends are coupled with two ends of the illumination lamp to form a driving circuit, and the connection terminal is connected to the driving circuit.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: December 22, 2020
    Assignee: SHANGHAI LUMIXESS LIGHTING TECHNOLOGY COMPANY
    Inventors: Xin Wu, Zhong Chen, Xinsheng Wang
  • Patent number: 10865210
    Abstract: This invention is in the area of synthesizing pyrimidine-based compounds useful in the treatment of disorders involving abnormal cellular proliferation, including but not limited to tumors and cancers.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 15, 2020
    Assignee: G1 Therapeutics, Inc.
    Inventors: Alexander Smith, Hannah S. White, Francis Xavier Tavares, Sergiy Krasutsky, Jian-Xie Chen, Roberta L. Dorrow, Hua Zhong
  • Patent number: 10867099
    Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Patent number: 10867986
    Abstract: A semiconductor device includes a fin structure, a first conductive line, a second conductive line and a first conductive rail. The fin structure is disposed on a substrate. The first conductive line is arranged to wrap a first portion of the fin structure. The second conductive line is attached on a second portion of the fin structure. The second portion is different from the first portion. The first conductive rail is disposed in a same layer as the first conductive line and the second conductive line on the substrate. The first conductive rail is attached on one end of the first conductive line and one end of the second conductive line for electrically connecting the first conductive line and the second conductive line.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shun-Li Chen, Chung-Te Lin, Hui-Zhong Zhuang, Pin-Dai Sue, Jung-Chan Yang
  • Patent number: 10867100
    Abstract: An integrated circuit designing system includes a non-transitory storage medium encoded with a first set of standard cell layouts and a second set of standard cell layouts both being configured to perform a predetermined function. The predetermined manufacturing process having a nominal minimum pitch (T) of metal lines. Each standard cell layout of the first set of standard cell layouts and the second set of standard cell layouts having a cell height (H) wherein the cell height is a non-integral multiple of the nominal minimum pitch. A hardware processor communicatively is coupled with the non-transitory storage medium and is configured to execute a set of instructions for generating an integrated circuit layout based on the first set of standard cell layouts, the second set of standard cell layouts and the nominal minimum pitch; and creating a data file corresponding to the integrated circuit layout.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Patent number: 10867114
    Abstract: An integrated circuit (IC) structure includes a first active region, a second active region, a first multi-gate structure, a first rail and a second rail. The first active region and the second active region extend in a first direction and are located at a first level. The second active region is separated from the first active region in a second direction. The first multi-gate structure extends in the second direction, overlaps the first active region and the second active region, and is located at a second level different from the first level. The first rail extends in the first direction, overlaps a portion of the first active region, supplies a first supply voltage, and is located at a third level. The second rail extends in the first direction, is located at the third level, is separated from the first rail in the second direction, and supplies a second supply voltage.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Zhong Zhuang, Ting-Wei Chiang, Lee-Chung Lu, Li-Chun Tien, Shun Li Chen
  • Publication number: 20200387469
    Abstract: A method for controlling a serial port information of a server host is provided. At first, a basic input/output system of the server host is activated. Then the BIOS reads a first port state value of a first input/output port of a MOS chip. Then an information output state of a serial port of a server host is determined according to the first port state value of the first input/output port, wherein the information output state is related to whether to output information of the serial port.
    Type: Application
    Filed: July 12, 2019
    Publication date: December 10, 2020
    Inventors: Jin CHEN, Yu-Xi CHEN, Zhong-Ying QU