Abstract: The present invention relates to improved protein-based biosensors that are suitable for detection of one or more target molecules in a sample. The biosensors are fully-reversible with dynamic ranges suitable for analytic and diagnostic applications. The biosensors of the present invention may be used in synthetic biology, for example in constructing artificial cellular or extracellular signalling networks.

Abstract: The invention relates to biosensors. More particularly, this invention relates to an electrochemical biosensor and to electrochemically active enzymes or variants thereof that are suitable for detection of one or more target molecules in a sample.

Abstract: A modular power unit (2; 200) for use with a power tool (1; 101; 102; 103) is provided. The modular power unit comprises a housing (3, 5, 7; 201); a motor (24); and a controller (23) arranged to control an operation of the motor (24), wherein the motor and the controller are at least partially enclosed by the housing. A power tool comprising the modular power unit is also provided.

Abstract: The invention relates to biosensors. More particularly, this invention relates to an electrochemical biosensor and to electrochemically active enzymes or variants thereof that are suitable for detection of one or more target molecules in a sample.

Abstract: A biosensor comprises an amino acid sequence of an enzyme such as glucose dehydrogenase which is capable of reacting with a substrate to produce one or more electrons, wherein the enzyme has been engineered to be switchable from a catalytically inactive to a catalytically active state in response to binding a target molecule. A method of detecting a target molecule is provided wherein an enzyme such as glucose dehydrogenase reacts with a substrate to produce one or more electrons as a result of the enzyme switching from a catalytically inactive to a catalytically active state in response to binding the target molecule.

Abstract: Described embodiments process data packets received that include a source address and at least one destination address. If the destination address is stored in a memory of an I/O adapter, the received data packet is processed in accordance with bridging rules associated with each destination address stored in the I/O adapter memory. If the destination address is not stored in the I/O adapter memory, the I/O adapter sends a task message to a processor to determine whether the destination address is stored in an address table stored in a shared memory of the network processor. The I/O adapter memory has lower access latency than the address table. If the destination address is stored in the address table, the received data packet is processed in accordance with bridging rules stored in the address table and the bridging rules stored in the I/O adapter memory are updated.

Abstract: An apparatus having a parser and a circuit is disclosed. The parser is configured to generate a source address, a destination address and information by parsing a packet received via one of a plurality of networks. The circuit is configured to search a plurality of memories in parallel during a single cycle of operation in the apparatus. The searching includes a plurality of lookups in the memories of a plurality of data sets associated with the source address, the destination address and the information, respectively. The circuit is also configured to bridge the packet between the networks in response to the data sets.

Abstract: A switch includes registers, a parser and port selection logic. The registers store an address in multiple locations. The address defines a bridge domain. Each bridge domain defines a set of switch ports. The parser identifies when a received frame includes a virtual local area network (VLAN) identifier. The parser uses the VLAN identifier to locate the address in the registers. The port selection logic is responsive to one of a first index from a first table that includes port identifiers and the bridge domain and a second index from a second table that includes VLAN identifiers. The switch is configured by defining an address scheme, inserting an address field in the first and second tables, and generating maps from the tables. The maps direct the port selection logic to direct received frames to desired port(s).

Abstract: An apparatus having a parser and a circuit is disclosed. The parser is configured to generate a source address, a destination address and information by parsing a packet received via one of a plurality of networks. The circuit is configured to search a plurality of memories in parallel during a single cycle of operation in the apparatus. The searching includes a plurality of lookups in the memories of a plurality of data sets associated with the source address, the destination address and the information, respectively. The circuit is also configured to bridge the packet between the networks in response to the data sets.

Abstract: The current invention provides methods for determining the estrogenic activity of a compound, which includes contacting an estrogen-responsive system having a gene under the control of a DMBT1 regulatory sequence with a test compound and determining how the test compound affects expression of the gene. The invention further provides for determining the progestogenic activity of a compound, which includes contacting an estrogen- and progesterone-responsive system having a gene under the control of a DMBT1 regulatory sequence with an estrogenic activity and a test compound and determining how the test compound effects expression of the gene. Nucleic acids and cell-based systems that include a portion of the DMBT1 regulatory sequence useful for these methods are also provided.