Abstract: The embodiments of the disclosure provide an intelligent glass and an intelligent window system, and relates to the technical field of window display. The intelligent glass of the disclosure includes a touch display assembly and a glass assembly. The touch display assembly is communicatively coupled to the glass assembly, and is configured to send a corresponding dimming instruction to the glass assembly based on a received touch instruction, such that the glass assembly adjusts its light transmittance based on the dimming instruction.

Abstract: A heat dissipation structure, includes: a lead frame, including a high temperature pad and a low temperature pad, the high temperature pad and the low temperature pad being two portions in the lead frame which are separated from each other, wherein a high heat generation component is disposed on the high temperature pad; and a high thermal conduction element, including two sides which are respectively directly connected with the high temperature pad and the low temperature pad, to dissipate the heat energy from the high heat generation component to the low temperature pad.

Abstract: A lead frame includes: at least one ductile structure, including a bond area, a die paddle, or a lead finger; and at least one sacrificial structure, connected between a corresponding ductile structure and a corresponding near portion in the lead frame, wherein the near portion is a portion of the lead frame close to the ductile structure.

Abstract: A dimming glass includes: a first base substrate and a second base substrate that are oppositely disposed, a dye liquid crystal layer disposed between the first base substrate and the second base substrate, and at least one temperature sensor disposed between the first base substrate and the second base substrate. The at least one temperature sensor is configured to detect a temperature of the dye liquid crystal layer.

Abstract: A fingerprint recognition detection circuit includes an operational amplifier, an integrating capacitor and a first switch connected in series, and a second switch. A non-inverting input terminal of the operational amplifier is coupled to a reference voltage terminal, and an inverting input terminal of the operational amplifier is coupled to a fingerprint sensing capacitor. The integrating capacitor and the first switch are coupled between the inverting input terminal of the operational amplifier and an output terminal of the operational amplifier. The second switch is coupled between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier.

Abstract: A touch display system includes: a piece of dimming glass; a transparent display screen provided on a side of the piece of dimming glass; an infrared touch apparatus; and a controller electrically connected to the piece of dimming glass, the display screen, and the infrared touch apparatus. The infrared touch apparatus is configured to generate an infrared detection net on a side of the display screen away from the piece of dimming glass; and the controller is configured to control the infrared touch apparatus to sense a touch action of a user, obtain a touch signal sensed by the infrared touch apparatus, and adjust a display image on the display screen and/or a light transmittance of the piece of dimming glass according to the touch signal.

Abstract: A temperature control system and a driving method thereof, and a liquid crystal apparatus are provided.

Abstract: The present disclosure relates to a dimming glass window assembly, and the dimming glass window assembly includes a window frame, and a dimming glass located in the window frame, where the dimming glass includes a first glass layer and a second glass layer which are opposite to each other and spaced apart, a dimming function layer and a sealant layer which are arranged between the first glass layer and the second glass layer, the dimming function layer is located in a sealed space bound by the sealant layer, the first glass layer and the second glass layer. The dimming glass further includes a control line unit connected to an external dimming controller, the control line unit includes: a flexible printed circuit, a first circuit board, a second circuit board and a signal line.

Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.

Abstract: A chip package unit includes: a base material; at least one chip, disposed on the base material; a package material, enclosing the base material and the chip; and at least one heat dissipation paste curing layer, formed by curing the heat dissipation paste, on a top side of the package material or a back side of the chip in a printed pattern.

Abstract: Described are various embodiments of a flight management method and system using same. In one embodiment, a digital flight management system comprises: a digital processing environment comprising instructions to access: flight request data related to a flight plan; aircraft parameter data; a flight risk data source; and geographical data. The instructions are executable to: calculate a predicted flight path; digitally compare the predicted flight path with flight risk data from the flight risk data source to assess a flight risk associated with the predicted flight path; and display via a user interface the predicted fight path in accordance with the flight risk.

Abstract: The present invention provides a chip packaging method, which includes: providing a base material, which includes plural finger contacts; disposing plural chips on the base material by flip chip mounting technology, and disposing plural vertical heat conducting elements surrounding each of the chips to connect the finger contacts on the base material; providing a packaging material to encapsulate the base material, the chips, and the vertical heat conducting elements; adhering a metal film on the packaging material via an adhesive layer, to form a package structure; and cutting the package structure into plural chip package units, wherein each of the chip package units includes one of the chips, a portion of the base material, a portion of the metal film, and a portion of the vertical heat conducting elements surrounding the chip.

Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A chip packaging structure includes: at least one semiconductor chip, having a signal processing function; a base material, wherein the semiconductor chip is disposed on the base material; at least one thermal conduction plate, disposed on the base material; and a package material, encapsulating the base material, the thermal conduction plate, and the semiconductor chip. The thermal conduction plate forms at least one thermal conduction channel in the package material.

Abstract: The present disclosure provides a light control glass and a method for detecting a tension thereof. The light control glass includes: two opposite glass substrates with a receiving space therebetween; and a tension detection circuit board in the receiving space. The light control glass further includes a first electromagnetic plug coupled to the tension detection circuit hoard, and a joint of the first electromagnetic plug is exposed from an outer edge of the two opposite glass substrates.

Abstract: The present invention provides a chip packaging method, which includes: providing a base material, which includes plural finger contacts; disposing plural chips on the base material by flip chip mounting technology, and disposing plural vertical heat conducting elements surrounding each of the chips to connect the finger contacts on the base material; providing a packaging material to encapsulate the base material, the chips, and the vertical heat conducting elements; adhering a metal film on the packaging material via an adhesive layer, to form a package structure; and cutting the package structure into plural chip package units, wherein each of the chip package units includes one of the chips, a portion of the base material, a portion of the metal film, and a portion of the vertical heat conducting elements surrounding the chip.

Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.

Abstract: A chip packaging method includes: providing plural chip units; providing a base material, and placing the chip units on the base material; providing an adhesive layer to adhere a metal foil to the chip unit, wherein the metal foil is a part of the base material or additional to the base material; and cutting the chip units on the base material to form plural separated chip package units, wherein each of the chip package units includes a cut metal foil part.

Abstract: A dimming glass includes: a first base substrate and a second base substrate that are oppositely disposed, a dye liquid crystal layer disposed between the first base substrate and the second base substrate, and at least one temperature sensor disposed between the first base substrate and the second base substrate. The at least one temperature sensor is configured to detect a temperature of the dye liquid crystal layer.