Abstract: A digital controller for a power factor correction (PFC) circuit, has first means for generating a first control signal for a switching transistor to avoid continuous oscillation between an inductor and parasitic capacitance of the switching transistor during discontinuous mode operation when an input voltage is less than substantially 50% of an output voltage. Second means generates a second control signal for a switching transistor to avoid continuous oscillation between an inductor and parasitic capacitance of the switching transistor during discontinuous mode operation when an input voltage is greater than substantially 50% of an output voltage. A power factor correction circuit and a method of operating a power factor correction circuit are also disclosed.