Abstract: A communication method is applied to a communication system using a forward error correction (FEC) technology. In the communication method, a header field of a first data transmission unit sent by a transmit end apparatus may indicate a modulation manner of a second data transmission unit after the first data transmission unit, so that a receive end apparatus can determine, based on the header field of the received first data transmission unit, the modulation manner of the second data transmission unit after the first data transmission unit. Then, before FEC decoding is performed on the second data transmission unit, the receive end apparatus may complete demodulation of the second data transmission unit based on the determined modulation manner such that FEC decoding can be performed on a header field and a load field of the second data transmission.

Abstract: Semiconductor structure and manufacturing method thereof are provided. The method includes providing a substrate provided with trenches spaced apart from each other and bit line structures spaced apart from each other, the bit line structures being at least partially located in the trenches; forming a first protection layer at least including a first side wall layer covering a side wall of each of the bit line structures and a second side wall layer covering a surface of each of the trenches; forming a second protection layer fully filling each of the trenches together with the first protection layer and at least including a silicon oxide layer formed by a thermal oxidation method; and forming a third protection layer at least covering a top surface, away from the substrate, of the second protection layer, the second and third protection layers covering a surface of the first side wall layer.

Abstract: A method includes the following operations for preparing a semiconductor structure, a semiconductor, and a semiconductor memory. A first dielectric layer and a first barrier layer are deposited on a substrate including an active area in sequence. A first mask including a first etching pattern is formed on the first barrier layer, and includes a groove extending in a first direction and uniformly distributed etching holes. Herein, the groove penetrates through the etching hole, and the depth of the etching hole is larger than that of the groove. Etching is performed along the first etching pattern, to remove the first barrier layer and etch the first dielectric layer to form a conductive channel.

Abstract: One embodiment provides an electroplating apparatus, which includes a tank filled with an electrolyte solution, a number of anodes situated around edges of the tank, a cathode situated above the tank, and a plurality of wafer-holding jigs attached to the cathode. A respective wafer-holding jig includes a common connector electrically coupled to the cathode and a pair of wafer-mounting frames electrically coupled to the common connector. Each wafer-mounting frame includes a plurality of openings, and a respective opening provides a mounting space for a to-be-plated solar cell, thereby facilitating simultaneous plating of front and back surfaces of the plurality of the solar cells.

Abstract: One embodiment provides an electroplating apparatus, which includes a tank filled with an electrolyte solution, a number of anodes situated around edges of the tank, a cathode situated above the tank, and a plurality of wafer-holding jigs attached to the cathode. A respective wafer-holding jig includes a common connector electrically coupled to the cathode and a pair of wafer-mounting frames electrically coupled to the common connector. Each wafer-mounting frame includes a plurality of openings, and a respective opening provides a mounting space for a to-be-plated solar cell, thereby facilitating simultaneous plating of front and back surfaces of the plurality of the solar cells.

Abstract: A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 ?. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces.

Abstract: A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 ?. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces.

Abstract: A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 ?. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces.

Abstract: A non-Flash non-volatile cross-trench memory array formed using an array of trenches formed back-end-of-the-line (BEOL) over a front-end-of-the-line (FEOL) substrate includes two-terminal memory elements operative to store at least one bit of data that are formed at a cross-point of a first trench and a second trench. The first and second trenches are arranged orthogonally to each other. At least one layer of memory comprises a plurality of the first and second trenches to form a plurality of memory elements. The non-volatile memory can be used to replace or emulate other memory types including but not limited to embedded memory, DRAM, SRAM, ROM, and FLASH. The memory is randomly addressable down to the bit level and erase or block erase operation prior to a write operation are not required.

Abstract: A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 ?. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces.

Abstract: A method of manufacturing a plurality of microelectronic packages including electrically and/or thermally conductive elements. The method includes providing a support structure having a plurality of protrusions and depressions extending outwardly from the support. A conductive element is then mated to the support structure in a male-to-female relationship. The depressions formed in the support structure and conductive element are used to house a microelectronic element such as a semiconductor chip. A substrate is provided so as to cover substantially each depression located in the conductive element. Leads interconnect contacts to the chip to terminals on the substrate. A curable encapsulant material may be deposited into the depression so as to protect and support the leads and the microelectronic element. Additionally, the curable encapsulant material forms part of the exterior of a single resulting chip package once the assembly is diced and cut into individual packages.

Abstract: A method of manufacturing a plurality of microelectronic packages including electrically and/or thermally conductive elements. The method includes providing a support structure having a plurality of protrusions and depressions extending outwardly from the support. A conductive element is then mated to the support structure in a male-to-female relationship. The depressions formed in the support structure and conductive element are used to house a microelectronic element such as a semiconductor chip. A substrate is provided so as to cover substantially each depression located in the conductive element. Leads interconnect contacts to the chip to terminals on the substrate. A curable encapsulant material may be deposited into the depression so as to protect and support the leads and the microelectronic element. Additionally, the curable encapsulant material forms part of the exterior of a single resulting chip package once the assembly is diced and cut into individual packages.