Patents by Inventor Zhong Lai Liu

Zhong Lai Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220247430
    Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
    Type: Application
    Filed: April 18, 2022
    Publication date: August 4, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Wei Bing Shang, Yu Zhang, Hong Wen Li, Yu Peng Fan, Zhong Lai Liu, En Peng Gao, Liang Zhang
  • Patent number: 11309919
    Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Wei Bing Shang, Yu Zhang, Hong Wen Li, Yu Peng Fan, Zhong Lai Liu, En Peng Gao, Liang Zhang
  • Publication number: 20200036396
    Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
    Type: Application
    Filed: October 4, 2019
    Publication date: January 30, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Wei Bing Shang, Yu Zhang, Hong Wen Li, Yu Peng Fan, Zhong Lai Liu, En Peng Gao, Liang Zhang
  • Patent number: 10447316
    Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wei Bing Shang, Yu Zhang, Hong Wen Li, Yu Peng Fan, Zhong Lai Liu, En Peng Gao, Liang Zhang
  • Publication number: 20160315639
    Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
    Type: Application
    Filed: December 19, 2014
    Publication date: October 27, 2016
    Inventors: Wei Bing Shang, Yu Zhang, Hong Wen Li, Yu Peng Fan, Zhong Lai Liu, En Peng Gao, Liang Zhang