Abstract: Provided are techniques for identifying and correcting model focus drift during model training. A model is trained using an original dataset with data, and the is classified into clusters. A representation is assigned to each of the clusters. A first visualization dashboard with visualizations is generated, where each visualization represents a first data distribution of an associated cluster using the representation assigned to that cluster. The model is fine-tuned using a fine-tune dataset. A second visualization dashboard is generated by updating each visualization, where each visualization represents a second data distribution of the associated cluster. It is determined that a cluster of the clusters has focus drift based on changes between the first data distribution and the second data distribution. The focus drift is corrected by: adding the data of the cluster to the fine-tune dataset to form a combined dataset and fine-tuning the model using the combined dataset.

Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.

Abstract: A microfluidic device includes first and second substrate structures. The first substrate structure has a first substrate surface configured to receive one or more droplets. A plurality of electrodes configured to apply an electric field to the droplets. The second substrate structure has a second substrate surface facing the first substrate surface and spaced apart from the first substrate surface to form a fluid channel. The microfluidic device has a first heating element adjacent to the first substrate structure and disposed on an opposite side of the first substrate surface, and a second heating element adjacent to the second substrate structure and disposed on an opposite side of the second substrate surface. The microfluidic device further includes one or more temperature sensors disposed adjacent to the fluid channel between the first substrate structure and the second substrate structure.

Abstract: A single-fiber bidirectional optical assembly includes an optical emitter, an optical receiver, a lens assembly, a first filter, a second filter, an optical power attenuator, and an optical fiber interface end. The optical fiber interface end is used for being connected to an optical fiber, a downlink optical signal emitted by the optical emitter is focused by the lens assembly and is then emitted to the optical fiber sequentially through the first filter and the optical fiber interface end and is transmitted by the optical fiber, and an uplink optical signal transmitted by the optical fiber passes through the second filter and is then received by the optical receiver. The optical power attenuator is arranged between the optical emitter and the optical fiber interface end, and the transmittance of the optical power attenuator varies with the wavelength of the optical signal.

Abstract: A semiconductor device includes a fin structure, a first conductive line, a second conductive line and a first conductive rail. The fin structure is disposed on a substrate. The first conductive line is arranged to wrap a first portion of the fin structure. The second conductive line is attached on a second portion of the fin structure. The second portion is different from the first portion. The first conductive rail is disposed in a same layer as the first conductive line and the second conductive line on the substrate. The first conductive rail is attached on one end of the first conductive line and one end of the second conductive line for electrically connecting the first conductive line and the second conductive line.

Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.

Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

Abstract: A parallel multi-step bio-reaction system(10) comprising: (a) a substrate arrangement(12) comprising a plurality of bio-reaction substrate holders(18) configured to hold a plurality of bio-reaction substrates(20); (b) a well arrangement(14) comprising a plurality of fluidic wells(22), the fluidic wells(22) corresponding to a plurality of steps of a multi-step bio-reaction; (c) an actuator(16) configured to: (i) move either the substrate arrangement(12) or the well arrangement(14) relative to the other of the substrate arrangement(12) or the well arrangement(14) to change the alignment of the bio-reaction substrates(20) as a group relative to the fluidic wells(22) as a group; and (ii) bring the bio-reaction substrates(20) into and out of contact with fluids in the fluidic wells(22).

Abstract: A transformer includes a bobbin and a plurality of coils wound on the bobbin. The plurality of coils includes a first primary coil; a second primary coil, located above the first primary coil and electrically connected to the first primary coil; a secondary coil, located between the first primary coil and the second primary; a first auxiliary coil, located above the second primary coil; and a second auxiliary coil, located on the first auxiliary coil and electrically connected to the first auxiliary coil.

Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.

Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

Abstract: Disclosed herein is a flexible sensing interface, comprising: a sensor, comprising: a core; an inner electrode in the form of a conductive material in contact with the core; an inner dielectric material substantially encasing the inner electrode; an outer electrode in the form of a conductive material in contact with the inner dielectric material and in electrical communication with the inner electrode; and an outer dielectric material substantially encasing the outer electrode; wherein the inner dielectric material and the outer dielectric material comprise an elastic material. Also disclosed herein are systems and methods for making and using the same.

Abstract: The present disclosure relates to a wide-range perpendicular sensitive magnetic sensor and the method for manufacturing the same, the magnetic sensor includes a substrate, a plurality of magnetic tunnel junctions, a plurality of magnetic flux regulators, a first output port and a second output port.

Abstract: The present disclosure relates to a wide-range perpendicular sensitive magnetic sensor and the method for manufacturing the same, the magnetic sensor includes a substrate, a plurality of magnetic tunnel junctions, a plurality of magnetic flux regulators, a first output port and a second output port.

Abstract: A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.

Abstract: A native NMOS device includes: a P-type epitaxial layer, a first and a second insulation region, a first P-type well, a second P-type well, a gate, an N-type source, and an N-type drain. The P-type epitaxial layer has a first concentration of P-type doped impurities. The first P-type well completely encompasses and is in contact with a lower surface of the N-type source. The second P-type well completely encompasses and is in contact with a lower surface of the N-type drain. Each of the first P-type well and the second P-type well has a second concentration of P-type doped impurities, and the second concentration of P-type doped impurities is higher than the first concentration of P-type doped impurities. The second concentration of P-type doped impurities is sufficient for preventing a leakage current from flowing between the N-type drain and the P-type substrate while the native NMOS device is in operation.

Abstract: A display substrate and a display device are provided. The display substrate includes a display region including light emitting units; the light emitting units are arranged into light emitting unit rows, and the light emitting units in one of the light emitting unit rows are arranged along a first direction; the light emitting units include first light emitting units. In at least part of the display region: distances, in the first direction, between a light emitting region of one first light emitting unit and light emitting regions of two of the first light emitting units adjacent to the one first light emitting units are different, and/or distances, in a second direction, between a light emitting region of one first light emitting units and the light emitting regions of two of the first light emitting units adjacent to the one first light emitting units are different.

Abstract: The present disclosure relates to an AC/DC closed-loop current sensor, including a magnetism gathering iron core, a TMR chip, a signal processing circuit, a signal generator, and a feedback coil. The TMR chip is arranged at an air gap of the magnetism gathering iron core and connected to the signal processing circuit. The signal processing circuit is connected to the signal generator. The feedback coil is wound around the magnetism gathering iron core and connected to the signal generator. The signal processing circuit is configured to select from the induced signal of the TMR chip and make an amplification to obtain a current signal component and send the current signal component to the signal generator. The signal generator is configured to adjust a current output to the feedback coil based on the current signal component, and output a measurement result of the selected current signal component.

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.

Abstract: The present disclosure relates to systems and methods for characterizing a behavior change of a process. A behavior model that can include a set of behavior parameters can be generated based on behavior data characterizing a prior behavior change of a process. A stimulus parameter for a performance test can be determined based on the set of behavior parameters. An application of the performance test to the process can be controlled based on the stimulus parameter to provide a measure of behavior change of the process. Response data characterizing one or more responses associated with the process during the performance test can be received. The set of behavior parameters can be updated based on the response data to update the behavior model characterizing the behavior change of the process. In some examples, the behavior model can be evaluated to improve or affect a future behavior performance of the process.