Abstract: An object of the invention is to mitigate effect of variations of electrical characteristics or other performances of amplifiers used in a driving circuit system and combat the so-called artifact such as stripe patterns in displayed images even in a case of the same gray-scale of display. A column electrode driving circuit 33 of the invention comprises: signal supply means (7, 8, 9, 10, 20) for outputting a plurality of multiplexed information signals in which column information signals to be applied to at least two column electrodes S1, S2, . . .

Abstract: Shorting bars are provided for electrostatic discharge protection as a portion of trace deposition in a photodiode array. During normal processing for etching of the metal layers, the shorting bars are removed without additional processing requirements. Additional shorting elements are provided by employing FET silicon layers having traces in contact with the array traces to provide extended ESD protection until removal of those shorting elements during normal processing for opening vias for photodiode bottom contact.

Abstract: Shorting bars are provided for electrostatic discharge protection as a portion of trace deposition in a photodiode array. During normal processing for etching of the metal layers, the shorting bars are removed without additional processing requirements. Additional shorting elements are provided by employing FET silicon layers having traces in contact with the array traces to provide extended ESD protection until removal of those shorting elements during normal processing for opening vias for photodiode bottom contact.

Abstract: A compensation circuit for use in a high resolution amplified flat panel for radiation imaging. The circuit includes an amplifier having an input terminal to receive amplified signal charge output on a source line by a selected pixel of the flat panel in response to a gate pulse. The amplified signal charge has a DC bias. Switching means is used to connect the input terminal to a potential voltage source when the amplified charge is received. The potential voltage source includes a magnitude substantially the same as the DC bias but opposite in polarity to offset the DC bias.

Abstract: A high resolution flat panel for radiation imaging includes an array of pixels arranged in rows and columns. Gate lines interconnect the pixels of the rows while source lines interconnect the pixels of the columns. Gate Driver circuits provide gate pulses to successive gate lines in response to input from a control circuit to select pixels on a row-by-row basis. The source lines lead to charge amplifiers that sense signal charges stored by the pixels when the pixels are selected. At least one pair of adjacent pixels in each row shares a source line. Gating of the pairs of pixels in the rows that share a source line is controlled by control logic to ensure that signal charges stored by only one of those pixels is applied to a shared source line at a time. This reduces the number of charge amplifiers in the flat panel while maintaining high resolution.

Abstract: Improved circuitry for active matix image arrays which, in one application reduces the number of source or gate lines for a given number of pixels, and in another application extends the dynamic range of the imaging array without reducing the number of source or gate lines. Each circuit includes multiple electrodes per pixel and multiple thin film transistors for switching charge from the pixel electrodes to the data line.

Abstract: Improved circuitry for active matrix image arrays which, in one application reduces the number of source or gate lines for a given number of pixels, and in another application extends the dynamic range of the imaging array without reducing the number of source or gate lines. Each circuit includes multiple electrodes per pixel and multiple thin film transistors for switching charge from the pixel electrodes to the data line.

Abstract: A high resolution flat panel for radiation imaging includes an array of pixels arranged in rows and columns. Gate lines interconnect the pixels of the rows while source lines interconnect the pixels of the columns. Gate driver circuits provide gate pulses to the gate lines in succession in response to input from a control circuit to select the pixels on a row-by-row basis. The source lines lead to charge amplifiers for sensing the signal charges stored by the pixels when the pixels are selected. At least one pair of adjacent pixels in each row of the array shares a source line. Gating of the pairs of pixels in the rows that share a source line is controlled by control logic to ensure that signal charges stored by only one of those pixels is applied to a shared source line at a time. This allows the number of charge amplifiers in the flat panel to be reduced while maintaining high resolution.

Abstract: A flat panel detector for radiation imaging includes an array of transistor switches each of which is associated with a pixel electrode. A radiation transducer including a top electrode and a radiation conversion layer is disposed over the array. Inhibiting mechanisms are positioned over dead zones between adjacent pixel electrodes to inhibit the accumulation of charge in the radiation conversion layer at the dead zones when the top electrode is biased and the flat panel detector is exposed to radiation. In one embodiment, the inhibiting mechanism is constituted by islands formed of semiconductor material between the array and the radiation transducer. Each island is positioned over a dead zone between adjacent pixel electrodes and contacts a pixel electrode to allow charges accumulated on the islands to drift to the pixel electrodes.

Abstract: A method of inhibiting electrostatic discharge damage to an array of semiconductor switches (21) formed on a common substrate and arranged in rows and columns comprises the steps of: during formation of gate lines (24) that interconnect one of the rows and columns of the array, connecting one end of each gate line directly to a shorting ring (52) and another end of each gate line to a shorting ring (56) via a protection element (54); during formation of the source lines (26) that interconnect the other of the rows or columns of the array, connecting one end of each source line directly to a shorting ring (56) and connecting another end of each source line to a shorting ring (56) via a protection element (58); and electrically coupling the shorting rings (52, 56). A semiconductor switch array (21) incorporating electrostatic discharge protection (50) is also provided.

Abstract: A thin-film, flat panel, pixelated detector array serving as a real-time digital imager and dosimeter for diagnostic or mega-voltage X rays or gamma rays, including a plurality of photodiodes (30) made of hydrogenated amorphous silicon arrayed in columns and rows upon a glass substrate (12). Each photodiode (30) is connected to a thin film field effect transistor (52) also located upon the glass or quartz substrate (12). Upper and lower metal contacts (38, 22) are located below and above the photodiodes (30) to provide the photodiodes (30) with a reverse bias. The capacitance of each photodiode (30) when multiplied by the resistance of the field effect transistor (52) to which it is connected yields an RC time constant sufficiently small to allow fluoroscopic or radiographic imaging in real time.

Abstract: In a method of fabricating a high resolution low voltage flat panel radiation imaging sensor having a radiation transducer having a radiation conversion layer of amorphous semiconductor and an electrode on one side thereof and an array of pixels arranged in rows and columns on an opposite side thereof, each pixel including a pixel electrode and storage capacitor and a charge readout device connected to the pixel electrode and the storage capacitor, the improvement comprising the step of shining light on selected regions of the radiation conversion layer which are aligned with the pixel electrodes to thereby crystallize the regions, resulting in a plurality of low resistivity and high charge mobility crystallized regions where the semiconductor material has been exposed to the light surrounded by high resistivity and low charge mobility regions where the semiconductor material has not been exposed to the light, for preventing lateral charge diffusion between respective ones of the low resistivity and high char

Abstract: A novel thin film transistor (TFT) structure for minimizing parasitic capitances on both the drain and source electrodes. According to a first embodiment, a triple gate TFT is provided with an open gate structure in which the source and drain electrodes are non-overlapping with the top gate electrode. A pair of bottom gate electrodes being aligned respectively with the first gap between the gate and source and the second gap between the gate and drain. According to a second embodiment of the invention, a full transfer TFT switch is provided having a source, a drain, a bottom gate and semi-conductor layer therebetween, and a partial top gate overlapping a portion of the drain and a portion of the semiconductor layer for creating a generally triangular-shaped charge density distribution in the semiconductor layer for moving channel electrons toward the source electrode.