Abstract: A cultivator tool includes a power head having a handle and a user interface. A motor is positioned within the power head and is configured to rotate a drive shaft about a drive axis. The cultivator further includes an attachment stem removably coupled to the power head at a first end and removably supporting a tool attachment unit at an opposite second end. A cover is receivable on the attachment stem between the tool attachment unit and the power head to cover a cutter rotatably supported on the tool attachment unit. The cover includes an aperture configured to receive a projection extending from the stem to limit rotation and sliding of the cover relative the tool attachment unit.

Abstract: The invention relates to inhibitors of glucosylceramide synthase (GCS) of the Formula I: represented by the following structural formula or a pharmaceutically acceptable salt thereof, wherein the variables are as defined herein, useful for the treatment of metabolic diseases, such as lysosomal storage diseases, either alone or in combination with enzyme replacement therapy, cystic disease and for the treatment of cancer.

Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.

Abstract: Energy efficiency and/or operational stability of a multistage compression system comprising a plurality (N) of centrifugal compressors that is compressing a gas feed having a variable flow rate is improved by adjusting reversibly the load on each compressor in response to changes in the flow rate of the gas feed using a main recycle system to enable operation of the centrifugal compressors at turndown capacity during periods when the flow rate is below total turndown capacity for all of the compressors, and if necessary, using the local recycle systems in order to avoid activation of anti-surge control, and switching one or more centrifugal compressors into low power mode or shutdown mode as required.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.

Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

Abstract: Controlling a capacity of the compression system in response to the variable incoming gas feed by: i) selectively varying a capacity of a first subset of one or more of the compressor trains by continuously varying the capacity of one or more cylinders of the one or more reciprocating compressor stages of the one or more compressor trains of the first subset between a maximum capacity and a minimum capacity; and/or ii) selectively varying a capacity of a second subset of one or more of the compressor trains by fully loading or fully unloading one or more cylinders of the one or more reciprocating compressor stages of the compressor trains of the second subset, wherein the first and second subsets are mutually exclusive.

Abstract: An industrial gas production plant operable to produce a feedstock gas at a variable production rate for supply to the downstream process; and a gas storage resource operable to store produced feedstock gas, the method comprising: determining the pressure of feedstock gas in a supply feed line to the downstream process; selectively controlling, using a control system, a flow of feedstock gas from the supply feed line to the gas storage resource or from the gas storage resource to the supply feed line in response to the determined pressure in order to regulate the pressure of the feedstock gas in the supply feed line to the downstream process at a predetermined set point pressure; and selectively controlling, using a control system, a flow rate of feedstock gas in the supply feed line to the downstream process in dependence upon at least one operational parameter of the gas storage resource.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor layer, a device layer, and heat dissipating structures. The semiconductor layer is over the substrate and the device layer is over the semiconductor layer. The device layer includes a first ohmic contact and a second ohmic contact. The heat dissipating structures are at least through the substrate and the semiconductor layer, and between the first ohmic contact and the second ohmic contact.

Abstract: A transistor structure is provided, the structure may be for a high electron mobility transistor (HEMT). The HEMT comprises a channel layer arranged over a substrate, the channel layer may have a top surface. A barrier layer may be arranged over the channel layer. A first opening may be in the barrier layer and extend partially into the channel layer. A first barrier liner may be arranged in the first opening and over the channel layer, the first barrier liner may have a bottom surface. The bottom surface of the first barrier liner may be lower than the top surface of the channel layer.

Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor device with a dual isolation structure and methods of manufacture. The structure includes: a dual isolation structure including semiconductor material; and an active device region including a channel material and a gate metal material over the channel material. The channel material is between the dual isolation structure and the gate metal material includes a bottom surface not extending beyond a sidewall of the dual isolation structure.

Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.

Abstract: Energy efficiency and/or operational stability of a multistage compression system comprising a plurality (N) of centrifugal compressors that is compressing a gas feed having a variable flow rate is improved by adjusting reversibly the load on each compressor in response to changes in the flow rate of the gas feed using a main recycle system to enable operation of the centrifugal compressors at turndown capacity during periods when the flow rate is below total turndown capacity for all of the compressors, and if necessary, using the local recycle systems in order to avoid activation of anti-surge control, and switching one or more centrifugal compressors into low power mode or shutdown mode as required.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.

Abstract: A method for a first vehicle to perform a neighbor discovery in an IP-based vehicular network is disclosed. The method includes, based on the first vehicle failed in a router discovery for a direct registration with an adjacent road-side unit (RSU), sending one or more first neighbor solicitation (NS) messages to a second vehicle; receiving, from the second vehicle, a first neighbor advertisement (NA) message as a response to the first NS message; and sending, to the second vehicle, a second NS message for registering the second vehicle as a relay vehicle based on the first NA message.

Abstract: The present disclosure provides a method for performing a handoff by a vehicle in an IP-based vehicular network, the method including: transmitting a first router solicitation (RS) message to a first road-side unit (RSU) to access the vehicular network, the first RS message including mobility information of the vehicle; and receiving a first router advertisement (RA) message from the first RSU as a response to the first RS message, the first RA message including a first prefix of the first RSU for configuring an address of the vehicle, wherein the vehicle performs a first address registration procedure based on the first prefix.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.