Patents by Inventor Zhong-Xiang He

Zhong-Xiang He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12322697
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.
    Type: Grant
    Filed: February 12, 2024
    Date of Patent: June 3, 2025
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Venkata Narayana Rao Vanukuru, Zhong-Xiang He
  • Patent number: 12317562
    Abstract: A transistor structure is provided, the structure may be for a high electron mobility transistor (HEMT). The HEMT comprises a channel layer arranged over a substrate, the channel layer may have a top surface. A barrier layer may be arranged over the channel layer. A first opening may be in the barrier layer and extend partially into the channel layer. A first barrier liner may be arranged in the first opening and over the channel layer, the first barrier liner may have a bottom surface. The bottom surface of the first barrier liner may be lower than the top surface of the channel layer.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: May 27, 2025
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Ramsey Hazbun, Anthony Stamper, Zhong-Xiang He, Pernell Dongmo
  • Publication number: 20250079345
    Abstract: Structures including a wide band-gap semiconductor layer stack and methods of forming such structures. The structure comprises a layer stack on a substrate and a first dielectric layer on the layer stack. The layer stack includes semiconductor layers that comprise a wide band-gap semiconductor material. A seal ring includes a trench that penetrates through the first dielectric layer and the layer stack to the substrate, a second dielectric layer that lines the trench, and a conductor layer including first and second portions inside the trench. The trench surrounds portions of the layer stack and the first dielectric layer. The second dielectric layer includes a first portion disposed between the first portion of the conductor layer and the portion of the layer stack, and the second dielectric layer includes a second portion disposed between the second portion of the conductor layer and the portion of the first dielectric layer.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 6, 2025
    Inventors: Ian McCallum-Cook, Mark Levy, Zhong-Xiang He
  • Publication number: 20250054908
    Abstract: Structures including a compound semiconductor layer stack and methods of forming such structures. The structure comprises a device region on a substrate. The device region includes a first section of a layer stack that has a plurality of semiconductor layers, and each semiconductor layer comprises a compound semiconductor material. The structure further comprises an isolation structure disposed about the section of the layer stack, and a device in the device region. The isolation structure penetrates through the layer stack to the substrate.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Inventors: Brett Cucci, Ramsey Hazbun, Richard Rassel, Zhong-Xiang He, Patrick Mitchell
  • Patent number: 12062574
    Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: August 13, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Zhong-Xiang He, Richard J. Rassel, Alvin J. Joseph, Ramsey M. Hazbun, Jeonghyun Hwang, Mark D. Levy
  • Publication number: 20240186240
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.
    Type: Application
    Filed: February 12, 2024
    Publication date: June 6, 2024
    Inventors: Venkata Narayana Rao VANUKURU, Zhong-Xiang HE
  • Patent number: 11942423
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: March 26, 2024
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Venkata Narayana Rao Vanukuru, Zhong-Xiang He
  • Patent number: 11916119
    Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: February 27, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Zhong-Xiang He, Jeonghyun Hwang, Ramsey M. Hazbun, Brett T. Cucci, Ajay Raman, Johnatan A. Kantarovsky
  • Publication number: 20230420326
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor layer, a device layer, and heat dissipating structures. The semiconductor layer is over the substrate and the device layer is over the semiconductor layer. The device layer includes a first ohmic contact and a second ohmic contact. The heat dissipating structures are at least through the substrate and the semiconductor layer, and between the first ohmic contact and the second ohmic contact.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Inventors: ZHONG-XIANG HE, RAMSEY HAZBUN, RAJENDRAN KRISHNASAMY, JOHNATAN AVRAHAM KANTAROVSKY, MICHEL ABOU-KHALIL, RICHARD RASSEL
  • Publication number: 20230155016
    Abstract: A transistor structure is provided, the structure may be for a high electron mobility transistor (HEMT). The HEMT comprises a channel layer arranged over a substrate, the channel layer may have a top surface. A barrier layer may be arranged over the channel layer. A first opening may be in the barrier layer and extend partially into the channel layer. A first barrier liner may be arranged in the first opening and over the channel layer, the first barrier liner may have a bottom surface. The bottom surface of the first barrier liner may be lower than the top surface of the channel layer.
    Type: Application
    Filed: November 16, 2021
    Publication date: May 18, 2023
    Inventors: RAMSEY HAZBUN, ANTHONY STAMPER, ZHONG-XIANG HE, PERNELL DONGMO
  • Publication number: 20230139011
    Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.
    Type: Application
    Filed: November 3, 2021
    Publication date: May 4, 2023
    Applicant: GlobalFoundries U.S. Inc.
    Inventors: Zhong-Xiang He, Jeonghyun Hwang, Ramsey M. Hazbun, Brett T. Cucci, Ajay Raman, Johnatan A. Kantarovsky
  • Publication number: 20230117591
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor device with a dual isolation structure and methods of manufacture. The structure includes: a dual isolation structure including semiconductor material; and an active device region including a channel material and a gate metal material over the channel material. The channel material is between the dual isolation structure and the gate metal material includes a bottom surface not extending beyond a sidewall of the dual isolation structure.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 20, 2023
    Inventors: Richard J. RASSEL, Johnatan A. KANTAROVSKY, Zhong-Xiang HE, Mark D. LEVY, Michel J. ABOU-KHALIL
  • Publication number: 20230034728
    Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Applicant: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Zhong-Xiang He, Richard J. Rassel, Alvin J. Joseph, Ramsey M. Hazbun, Jeonghyun Hwang, Mark D. Levy
  • Publication number: 20220399270
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.
    Type: Application
    Filed: June 9, 2021
    Publication date: December 15, 2022
    Inventors: Venkata Narayana Rao VANUKURU, Zhong-Xiang HE
  • Patent number: 11380615
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: July 5, 2022
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Daisy A. Vaughn, Stephen R. Bosley, Zhong-Xiang He
  • Publication number: 20210134716
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.
    Type: Application
    Filed: December 11, 2020
    Publication date: May 6, 2021
    Inventors: Anthony K. STAMPER, Daisy A. VAUGHN, Stephen R. BOSLEY, Zhong-Xiang HE
  • Patent number: 10910304
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: February 2, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Daisy A. Vaughn, Stephen R. Bosley, Zhong-Xiang He
  • Publication number: 20200243439
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.
    Type: Application
    Filed: January 24, 2019
    Publication date: July 30, 2020
    Inventors: Anthony K. STAMPER, Daisy A. VAUGHN, Stephen R. BOSLEY, Zhong-Xiang HE
  • Publication number: 20190362977
    Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.
    Type: Application
    Filed: August 7, 2019
    Publication date: November 28, 2019
    Inventors: Jeffrey P. GAMBINO, Thomas J. HARTSWICK, Zhong-Xiang HE, Anthony K. STAMPER, Eric J. WHITE
  • Patent number: 10438803
    Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: October 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Thomas J. Hartswick, Zhong-Xiang He, Anthony K. Stamper, Eric J. White