Abstract: A power amplifying apparatus is provided. A reference signal generator provides a reference signal having an enabling state and a disabling state. A digital power amplifier generates a current based on the reference signal and an input signal. An output signal of the digital power amplifier is related to the current. When the reference signal is in the enabling state, the current is related to the input signal. When the reference signal is in the disabling state, the current is irrelevant to the input signal. During the enabling state of the reference signal, a data generator provides an output alternating between an in-phase signal and a quadrature-phase signal as the input signal to the digital power amplifier. When the reference signal is in the disabling state, the data generator provides a fixed signal as the input signal to the digital power amplifier.

Abstract: A power amplifying apparatus is provided. A reference signal generator provides a reference signal having an enabling state and a disabling state. A digital power amplifier generates a current based on the reference signal and an input signal. An output signal of the digital power amplifier is related to the current. When the reference signal is in the enabling state, the current is related to the input signal. When the reference signal is in the disabling state, the current is irrelevant to the input signal. During the enabling state of the reference signal, a data generator provides an output alternating between an in-phase signal and a quadrature-phase signal as the input signal to the digital power amplifier. When the reference signal is in the disabling state, the data generator provides a fixed signal as the input signal to the digital power amplifier.

Abstract: A method comprises forming a first semiconductor device in a substrate, where the first semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness, and raised source and drain regions disposed on either side of the gate structure. The method further comprises forming a second semiconductor device in the substrate and electrically isolated from the first semiconductor device, where the second semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a second thickness less than the first thickness of the spacer of the first semiconductor device, and recessed source and drain regions disposed on either side of the gate structure.

Abstract: A one transistor (1T-RAM) bit cell and method for manufacture are provided. A metal-insulator-metal (MIM) capacitor structure and method of manufacturing it in an integrated process that includes a finFET transistor for the 1T-RAM bit cell is provided. In some embodiments, the finFET transistor and MIM capacitor are formed in a memory region and an asymmetric processing method is disclosed, which allows planar MOSFET transistors to be formed in another region of a single device. In some embodiments, the 1T-RAM cell and additional transistors may be combined to form a macro cell, multiple macro cells may form an integrated circuit. The MIM capacitors may include nanoparticles or nanostructures to increase the effective capacitance. The finFET transistors may be formed over an insulator. The MIM capacitors may be formed in interlevel insulator layers above the substrate. The process provided to manufacture the structure may advantageously use conventional photomasks.

Abstract: A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).

Abstract: A semiconductor device includes a substrate, a first device situated on the substrate, the first device including a source and a drain each situated extending a first depth within the substrate, and a second device situated on the substrate, the second device including a source and a drain each situated extending a second depth within the substrate, the second depth not equal to the first depth.

Abstract: A method comprises forming a first semiconductor device in a substrate, where the first semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness, and raised source and drain regions disposed on either side of the gate structure. The method further comprises forming a second semiconductor device in the substrate and electrically isolated from the first semiconductor device, where the second semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a second thickness less than the first thickness of the spacer of the first semiconductor device, and recessed source and drain regions disposed on either side of the gate structure.

Abstract: An integrated high-speed package comprising a package housing having a housing lip and connector having a center pin abutting along a bottom surface of the housing lip. For signal registration of a first substrate to the signal lead, the substrate is “floated” up to the housing lip, which provides an alignment reference to ensure that the top surface of the first substrate is aligned and in direct registration with the signal lead. In another embodiment, the center pin to substrate registration is provided at a top surface of a housing base. The housing base preferably comprises a first portion of a first height and a second portion of a second height. Accordingly, the housing base can accommodate substrates of different thickness while allowing a top surface of the first and a second substrate to be coplanar to facilitate signal registration there between.

Abstract: A differential amplifier or delay cell for use in a voltage controlled oscillator comprises a pair of clipper transistors coupled across the output nodes of the amplifier for limiting the voltage swing of the output to a transistor threshold and improving the frequency response of the amplifier. A cross-coupled pair of transistors are included to provide a hysteresis response further improving the noise immunity of the amplifier. A variable control voltage is converted to a current and used to control the frequency of the output signal. An oscillator is formed from three stages, cascaded together, each stage comprising the improved differential amplifier and controlled by a differential reference signal.

Abstract: A high speed CMOS current switching circuit suitable for use in digital to analog converters for graphic interfaces having high pixel clock rates, and such interfaces as may be used in portable and other battery operated or low power consumption applications. In operation, the current switching circuit normally steers an idle current to ground. If the bit of the digital to analog converter input digital signal represented by the respective source is a 1, the input signal representing the bit is delayed slightly while the current steered to ground is increased from the idle value to the full desired output current, whereupon at the end of the delay, the device coupling the output current to ground is turned off, thereby forcing the output current through an output device. A low power current steering circuit which can perform dynamic current steering without affecting switching speed performance is also disclosed.

Abstract: A high speed CMOS current switching circuit suitable for use in digital to analog converters for graphic interfaces having high pixel clock rates (high display resolutions), and such interfaces as may be used in portable and other battery operated or low power consumption applications. In operation, the current switching circuit normally steers an idle current to ground. If the bit of the digital to analog converter input digital signal represented by the respective source is a 1, the input signal representing the bit is delayed slightly while the current steered to ground is increased from the idle value to the full desired output current, whereupon at the end of the delay, the device coupling the output current to ground is turned off, thereby forcing the output current through an output device.