Abstract: The present disclosure relates to a totem pole bridgeless power factor correction device and a power supply system. The device includes a power factor correction module. The power factor correction module includes a first transistor, a second transistor, a third transistor, a fourth transistor, an inductor and a control module for generating a zeroth control signal in the first time period to control the third transistor and the fourth transistor to be in an off state, performing a zero-crossing detection on an AC voltage in the first time period, generating a first control signal to control a conduction state of the first transistor and the second transistor before the AC voltage crosses zero, and generating a second control signal to control the conduction state of the first transistor and the second transistor after the AC voltage crosses zero.

Abstract: A device is configured to detect a zero voltage switching (ZVS) circuit output that includes a hard switching signal. The hard switching signal includes a false signal and a spike signal. Thereafter, the device generates digital pulse signals that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal, and uses the digital pulse signal that corresponds to the spike signal for adjusting a timing of a pulse width modulation (PWM) switching cycle.

Abstract: An apparatus includes a capacitor coupled to a gate of a power switch, and a negative voltage adjustment device connected to a common node of the capacitor and the gate of the power switch, wherein the negative voltage adjustment device is configured such that after a turn-off signal is applied to the gate of the power switch, a voltage across the capacitor is maintained at a predetermined voltage level through a negative current provided by the negative voltage adjustment device.

Abstract: An apparatus includes a capacitor coupled to a power switch, wherein the capacitor is configured to provide a negative gate voltage to the power switch when a turn-off signal is applied to a gate of the power switch, and a sink and source power supply coupled to the capacitor, wherein the sink and source power supply has a first current limit for controlling a sink current flowing from the capacitor to the sink and source power supply, and a second current limit for controlling a source current flowing from the sink and source power supply to the capacitor.

Abstract: An apparatus includes a power converter configured to provide a constant current charge to a capacitor coupled to a high voltage bus through a mechanical contact, an isolation interface configured to receive a pre-charge signal on a primary side of the isolation interface, and convert the pre-charge signal into a bias voltage signal and a control command signal on a secondary side of the isolation interface, and based on the bias voltage signal and the control command signal, a constant current control unit configured to generate a gate drive signal for the power converter.

Abstract: The invention relates to the field of power semiconductor devices. This invention discloses a drive circuit and device of a power switch. The input terminal of the drive circuit receives a pulse signal; the output terminal of the drive circuit is connected to a capacitor circuit. The capacitor circuit is used to provide a negative voltage for a first electrode of the power switch to turn off the power switch when the pulse signal is a turn-off signal; the drive circuit includes a capacitance adjustment unit. The capacitance adjustment unit includes a negative voltage adjustment element that can charge a capacitor whose voltage is lower than a predetermined voltage when the pulse signal is the turn-off signal.

Abstract: The present disclosure relates to a totem pole bridgeless power factor correction device and a power supply system. The device includes a power factor correction module. The power factor correction module includes a first transistor, a second transistor, a third transistor, a fourth transistor, an inductor and a control module for generating a zeroth control signal in the first time period to control the third transistor and the fourth transistor to be in an off state, performing a zero-crossing detection on an AC voltage in the first time period, generating a first control signal to control a conduction state of the first transistor and the second transistor before the AC voltage crosses zero, and generating a second control signal to control the conduction state of the first transistor and the second transistor after the AC voltage crosses zero.

Abstract: An apparatus includes a capacitor coupled to a gate of a power switch, and a negative voltage adjustment device connected to a common node of the capacitor and the gate of the power switch, wherein the negative voltage adjustment device is configured such that after a turn-off signal is applied to the gate of the power switch, a voltage across the capacitor is maintained at a predetermined voltage level through a negative current provided by the negative voltage adjustment device.

Abstract: The invention relates to the field of power semiconductor devices. This invention discloses a drive circuit and device of a power switch. The input terminal of the drive circuit receives a pulse signal; the output terminal of the drive circuit is connected to a capacitor circuit. The capacitor circuit is used to provide a negative voltage for a first electrode of the power switch to turn off the power switch when the pulse signal is a turn-off signal; the drive circuit includes a capacitance adjustment unit. The capacitance adjustment unit includes a negative voltage adjustment element that can charge a capacitor whose voltage is lower than a predetermined voltage when the pulse signal is the turn-off signal.

Abstract: The invention relates to the field of power semiconductor devices. This invention discloses a drive circuit and device of a power switch. The input terminal of the drive circuit receives a pulse signal; the output terminal of the drive circuit is connected to a capacitor circuit. The capacitor circuit is used to provide a negative voltage for a first electrode of the power switch to turn off the power switch when the pulse signal is a turn-off signal; the drive circuit includes a capacitance adjustment unit. The capacitance adjustment unit includes a negative voltage adjustment element that can charge a capacitor whose voltage is lower than a predetermined voltage when the pulse signal is the turn-off signal.

Abstract: A device is configured to detect a zero voltage switching (ZVS) circuit output that includes a hard switching signal. The hard switching signal includes a false signal and a spike signal. Thereafter, the device generates digital pulse signals that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal, and uses the digital pulse signal that corresponds to the spike signal for adjusting a timing of a pulse width modulation (PWM) switching cycle.

Abstract: A device [200] is configured to detect a zero voltage switching (ZVS) circuit [110] output that includes a hard switching signal. The hard switching signal [114] includes a false signal [116] and a spike signal [118]. Thereafter, the device generates digital pulse signals [312/314] that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal [312], and uses the digital pulse signal [314] that corresponds to the spike signal for adjusting a timing [132] of a pulse width modulation (PWM) switching cycle [Vgs ].

Abstract: The invention relates to the field of power semiconductor devices. This invention discloses a drive circuit and device of a power switch. The input terminal of the drive circuit receives a pulse signal; the output terminal of the drive circuit is connected to a capacitor circuit. The capacitor circuit is used to provide a negative voltage for a first electrode of the power switch to turn off the power switch when the pulse signal is a turn-off signal; the drive circuit includes a capacitance adjustment unit. The capacitance adjustment unit includes a negative voltage adjustment element that can charge a capacitor whose voltage is lower than a predetermined voltage when the pulse signal is the turn-off signal.

Abstract: An apparatus includes an alternating current (AC) input node. The apparatus also includes a power factor correction (PFC) circuit with a first inductor coupled between the AC input node and a switch node. The apparatus also includes a switching analysis circuit for the PFC circuit. The switching analysis circuit includes a second inductor inductively coupled to the first inductor. The switching analysis circuit also includes a rectifier coupled to the second inductor. The switching analysis circuit also includes a sensing resistor coupled to the rectifier.

Abstract: An apparatus includes an alternating current (AC) input node. The apparatus also includes a power factor correction (PFC) circuit with a first inductor coupled between the AC input node and a switch node. The apparatus also includes a switching analysis circuit for the PFC circuit. The switching analysis circuit includes a second inductor inductively coupled to the first inductor. The switching analysis circuit also includes a rectifier coupled to the second inductor. The switching analysis circuit also includes a sensing resistor coupled to the rectifier.

Abstract: A multiple-output integrated power factor correction system includes, for example, a processor that is formed in a substrate and is arranged to monitor each voltage output of two or more output stages of a power supply and in response to generate an individual voltage error signal for each monitored output stage. A combined output voltage error signal is generated in response to each of the individual voltage error signals. The voltage input to the power supply and the total inductor current of the power supply are monitored and used to generate a combined output voltage control signal in response to the monitored input voltage total inductor current as well as the combined output voltage error control signal. Each individual output voltage control signal for each monitored output stage is generated in response to each of the respective generated individual voltage error signals.

Abstract: A device [200, para. 24] is configured to detect a zero voltage switching (ZVS) circuit [110, para. 14] output that includes a hard switching signal. The hard switching signal [114, para. 16] includes a false signal [116, para. 16] and a spike signal [118, para. 16]. Thereafter, the device generates digital pulse signals [312/314, para. 39] that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal [312, para. 41], and uses the digital pulse signal [314, para. 42] that corresponds to the spike signal for adjusting a timing [132, para. 20] of a pulse width modulation (PWM) switching cycle [Vgs 106, para. 32].

Abstract: A circuit includes a zero current detector (ZCD) circuit that senses an inductor current of an inductor and generates signal pulses indicating when an increasing cycle of the inductor current crosses a predetermined current value and when a decreasing cycle of the inductor current crosses the predetermined current value. A sync control provides a control signal specifying one of the signal pulses corresponding to the increasing or decreasing cycle of the inductor current. A sync selector circuit generates a sync pulse representing the signal pulse from the ZCD in response to the control signal. The sync pulse triggers a timing adjustment for a switch device.

Abstract: A multiple-output integrated power factor correction system includes, for example, a processor that is formed in a substrate and is arranged to monitor each voltage output of two or more output stages of a power supply and in response to generate an individual voltage error signal for each monitored output stage. A combined output voltage error signal is generated in response to each of the individual voltage error signals. The voltage input to the power supply and the total inductor current of the power supply are monitored and used to generate a combined output voltage control signal in response to the monitored input voltage total inductor current as well as the combined output voltage error control signal. Each individual output voltage control signal for each monitored output stage is generated in response to each of the respective generated individual voltage error signals.

Abstract: A multiple-output integrated power factor correction system includes, for example, a processor that is formed in a substrate and is arranged to monitor each voltage output of two or more output stages of a power supply and in response to generate an individual voltage error signal for each monitored output stage. A combined output voltage error signal is generated in response to each of the individual voltage error signals. The voltage input to the power supply and the total inductor current of the power supply are monitored and used to generate a combined output voltage control signal in response to the monitored input voltage total inductor current as well as the combined output voltage error control signal. Each individual output voltage control signal for each monitored output stage is generated in response to each of the respective generated individual voltage error signals.