Abstract: The present invention relates to a preparation method of a P-type high-resistance and ultra-high-resistance Czochralski monocrystalline silicon substrate. According to the present invention, an oxygen concentration in a silicon wafer is controlled to match with a resistivity, so as to realize that a conductive type of the silicon substrate does not change after a device is manufactured, and that the silicon substrate has a high resistivity. The oxygen concentration and the resistivity in silicon crystal can be adjusted separately or together; and operation is flexible, and a yield of a high-resistance silicon crystal is greatly improved.

Abstract: The present disclosure relates to a method for improving the surface roughness of a SOI wafer. By controlling the gas composition at each stage of the rapid thermal treatment process and corresponding heating and annealing processes, the final wafer is enabled to have a surface roughness of less than 5? and has good application prospects.

Abstract: The present disclosure relates to a method for treating a wafer surface. By controlling the gas composition at each stage of the treatment process, and corresponding processes of heating and annealing, and cooling and thinning by oxidation, the final wafer is enabled to have a surface roughness of less than 5 ?. This effectively reduces the cost of the final treatment process and has good application prospects.

Abstract: A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.

Abstract: A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.