Abstract: The application discloses a device and a method for picking up top k values from N values. The method comprises: A) controlling a buffer to receive values into a data pool until the number of values in the data pool reaches the predetermined memory size; B) dividing the values in the data pool into a first portion and a second portion; C) discarding the values in the second portion and controlling the buffer to continue to receive values into the data pool; D) repeating steps B to C until the buffer has received all the N values; E) dividing the values in the data pool into the first portion and the second portion until the number of values in the first portion reaches k; and F) controlling the buffer to output the k values in the first portion as the top k values.

Abstract: A method for obtaining board parameters of a printed circuit board, including the following steps: obtaining parameter information of a stripline on the printed circuit board; obtaining physical parameters of the stripline based on the parameter information of the stripline and a predetermined electromagnetic simulation application; calculating required board parameters of the printed circuit board based on the parameter information and the physical parameters of the stripline. In the present disclosure, the physical parameters of the stripline are obtained based on the physical nature of the stripline on the printed circuit board, and there is no need for fitting or adopting a hypothetical model in order to obtain board parameters corresponding to each frequency point of the stripline; the present disclosure is simple and straightforward during operation, and the obtained board parameters of the printed circuit board are highly accurate.

Abstract: The disclosure provides a glitch removal circuit with low latency. The glitch removal circuit includes a first signal edge detector, a second signal edge detector, a latch, and a control signal generator. The first signal edge detector is activated according to the first control signal to detect the rising edge of the input signal to generate the first detection result. The second signal edge detector is activated according to the second control signal to detect the falling edge of the input signal to generate the second detection result. The latch sets the generated output signal according to the first detection result, and clears the generated output signal according to the second detection result. The control signal generator shields the glitch on the input signal to generate a processed signal, and generates a first control signal and a second control signal according to the processed signal.

Abstract: The disclosure provides a glitch removal circuit with low latency. The glitch removal circuit includes a first signal edge detector, a second signal edge detector, a latch, and a control signal generator. The first signal edge detector is activated according to the first control signal to detect the rising edge of the input signal to generate the first detection result. The second signal edge detector is activated according to the second control signal to detect the falling edge of the input signal to generate the second detection result. The latch sets the generated output signal according to the first detection result, and clears the generated output signal according to the second detection result. The control signal generator shields the glitch on the input signal to generate a processed signal, and generates a first control signal and a second control signal according to the processed signal.

Abstract: A low latency retimer and a low latency control method are provided; a physical layer module is provided on each of two opposite sides of the retimer; each physical layer module includes at least one set of signal transceiver units including a signal receiving unit and a signal transmitting unit; the signal receiving unit performs a serial-to-parallel conversion on a first high-speed serial signal to generate a parallel signal, and sends the parallel signal to the signal transmitting unit; the signal transmitting unit performs a parallel-to-serial conversion on the parallel signal, to convert the parallel signal to obtain a second high-speed serial signal, and outputs the second high-speed serial signal. Data paths of the retimer form a loopback structure, and the signal transmitting unit and the signal receiving unit are physically adjacent to each other, which solves the problem of signal transmission delay, and avoids high power consumption.

Abstract: A method for obtaining board parameters of a printed circuit board, including the following steps: obtaining parameter information of a stripline on the printed circuit board; obtaining physical parameters of the stripline based on the parameter information of the stripline and a predetermined electromagnetic simulation application; calculating required board parameters of the printed circuit board based on the parameter information and the physical parameters of the stripline. In the present disclosure, the physical parameters of the stripline are obtained based on the physical nature of the stripline on the printed circuit board, and there is no need for fitting or adopting a hypothetical model in order to obtain board parameters corresponding to each frequency point of the stripline; the present disclosure is simple and straightforward during operation, and the obtained board parameters of the printed circuit board are highly accurate.

Abstract: The application discloses a device and a method for picking up top k values from N values.

Abstract: A test device and method with built-in self-test logic and a communication device. The test device includes at least one generator and at least one checker which are disposed between a physical layer and a medium access control layer. The at least one generator is configured to generate a protocol pattern to form a data path between the physical layer and the medium access control layer, and generate different pseudo random bit sequence patterns in the data path. The at least one checker is configured to test a data stream in the physical layer and/or the medium access control layer according to the pseudo random bit sequence patterns, thereby locating a fault position.

Abstract: The application discloses a memory controller coupled to a memory module for controlling access to the memory module. The memory controller comprises: a registering clock driver coupled to the memory module for providing a data access command to the memory module so as to control access to the memory module; and a data buffer coupled between the registering clock driver and the memory module for exchanging data between the memory module and the registering clock driver under the control of the registering clock driver; wherein the registering clock driver comprises a computing unit for computing the data received via the data buffer from the memory module and providing a computing result to the memory module via the data buffer.

Abstract: The present application discloses a test device and method with built-in self-test logic and a communication device. The test device includes at least one generator and at least one checker which are disposed between a physical layer and a medium access control layer, The at least one generator is configured to generate a protocol pattern to form a data path between the physical layer and the medium access control layer and generate different pseudo random bit sequence patterns in the data path. The at least one checker is configured to test data stream in the physical layer and/or the medium access control layer according to the pseudo random bit sequence patterns, thereby locating a fault position.

Abstract: The present disclosure provides a communication device and a skew correction method thereof. The communication device includes a first signal transceiving device and a correction device. The correction device is coupled to the first signal transceiving device through multiple first channels in a correction mode, each of the first channels has multiple first sub-channels. In the correction mode, the first signal transceiving device simultaneously transmits multiple first data through all the first sub-channels of first channels, and the correction device receives the first data through all the first sub-channels to calculate first skew differences of all the first sub-channels, thus calculating first skew differences according to the first skew values.

Abstract: A fast phase frequency includes two fast pulsed-latches, a NAND gate, and an adjustable delay circuit, where the fast pulsed-latches include a pulse generating circuit, a reset circuit, and an output latch circuit. The pulse generating circuit is configured to generate a power supply pulse signal when a rising edge of the clock signal arrives, the power supply pulse signal causing the input of the output latch circuit to be a low level. The output latch circuit is configured to maintain its current output state when the clock signal or the reset signal is invalid, and the reset circuit is configured to set the input of the output latch circuit to be a high level. By using fast pulsed-latches with clock and reset control, the fast phase frequency detector shortens the reset loop delay and increases the maximum operating frequency of the phase frequency detector.

Abstract: A time-to-digital converter and a phase difference detection method are disclosed. The time-to-digital converter includes a detection unit and a digital control circuit. The detection unit comprising: a phase detection circuit, a first and a second clock signal are respectively coupled to an identical input terminal of the phase detection circuit and a reference signal is coupled to another input terminal of the phase detection circuit; the phase detection circuit is configured to output a pulse width corresponding to a phase difference between the first or the second clock signal and the reference signal; a filter circuit, coupled to an output terminal of the phase detection circuit; a ring oscillator circuit, coupled to an output terminal of the filter circuit and configured to output an oscillation clock signal corresponding to the pulse width. The digital control circuit is configured to provide the reference signal and receive the oscillation clock signal.

Abstract: A time-to-digital converter and a phase difference detection method are disclosed. The time-to-digital converter includes a detection unit and a digital control circuit. The detection unit comprising: a phase detection circuit, a first and a second clock signal are respectively coupled to an identical input terminal of the phase detection circuit and a reference signal is coupled to another input terminal of the phase detection circuit; the phase detection circuit is configured to output a pulse width corresponding to a phase difference between the first or the second clock signal and the reference signal; a filter circuit, coupled to an output terminal of the phase detection circuit; a ring oscillator circuit, coupled to an output terminal of the filter circuit and configured to output an oscillation clock signal corresponding to the pulse width. The digital control circuit is configured to provide the reference signal and receive the oscillation clock signal.

Abstract: The application discloses a memory controller coupled to a memory module for controlling access to the memory module. The memory controller comprises: a registering clock driver coupled to the memory module for providing a data access command to the memory module so as to control access to the memory module; and a data buffer coupled between the registering clock driver and the memory module for exchanging data between the memory module and the registering clock driver under the control of the registering clock driver; wherein the registering clock driver comprises a computing unit for computing the data received via the data buffer from the memory module and providing a computing result to the memory module via the data buffer.

Abstract: Disclosed a fast phase frequency detector, comprising: two fast pulsed-latches, a NAND gate and an adjustable delay circuit. The fast pulsed-latches comprises: a pulse generating circuit, a reset circuit, and an output latch circuit; the pulse generating circuit is configured to generate a power supply pulse signal when a rising edge of the clock signal arrives, the power supply pulse signal causing the input of the output latch circuit to be a low level; the output latch circuit is configured to maintain its current output state when the clock signal or the reset signal is invalid; the reset circuit is configured to set the input of the output latch circuit to be a high level. By using fast pulsed-latches with clock and reset control, the fast phase frequency detector of the present application shortens the reset loop delay and increases the maximum operating frequency of the phase frequency detector.

Abstract: A voltage-mode line driving circuit is provided. The voltage-mode line driving circuit includes a driving circuit, the driving circuit receiving, as an input signal, a feedback signal, and outputting an output signal. The voltage-mode line driving signal also includes an adaptive tuning circuit coupled to the driving circuit, the adaptive tuning circuit receiving as input signals the feedback signal and the output signal and adaptively outputting a modifying signal to the driving circuit which modifies the feedback signal.

Abstract: A ring oscillator is disclosed for generating one or more clock signals. In some embodiments, the ring oscillator includes a first set of n series coupled inverters, a second set of n series coupled inverters, a first reset switch configured to couple a last inverter of the first set of inverters to a first inverter of the second set of inverters and to generate a first signal edge, a second reset switch configured to couple a last inverter of the second set of inverters to a first inverter of the first set of inverters, and a cross-coupling circuit coupled between an output of an inverter of the first set of inverters to a corresponding output of an inverter of the second set of inverters. In some embodiments, 2n clock signals separated in phase by 360°/2n may be generated.

Abstract: A voltage-mode line driving circuit is provided. The voltage-mode line driving circuit includes a driving circuit, the driving circuit receiving, as an input signal, a feedback signal, and outputting an output signal. The voltage-mode line driving signal also includes an adaptive tuning circuit coupled to the driving circuit, the adaptive tuning circuit receiving as input signals the feedback signal and the output signal and adaptively outputting a modifying signal to the driving circuit which modifies the feedback signal.

Abstract: A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PFD signals. Pulse blocking circuitry is utilized to provide first and second output signals based on the first and second pulsed signals respectively, wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted. By reducing the time the first and second output signals are simultaneously asserted, the effects of charge pump current source mismatch are minimized and static phase error is reduced.