Abstract: A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g., 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).

Abstract: The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

Abstract: A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices.

Abstract: A method is provided for making a semiconductor device, comprising (a) providing a semiconductor stack comprising a first semiconductor layer (407) having a <110> crystallographic orientation and a second semiconductor layer (405) having a <100> crystallographic orientation; (b) defining an oxide mask (415) in the first semiconductor layer; and (c) utilizing the oxide mask to pattern the second semiconductor layer.

Abstract: A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

Abstract: The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

Abstract: A method is provided for making a semiconductor device, comprising (a) providing a semiconductor stack comprising a first semiconductor layer (407) having a <110> crystallographic orientation and a second semiconductor layer (405) having a <100> crystallographic orientation; (b) defining an oxide mask (415) in the first semiconductor layer; and (c) utilizing the oxide mask to pattern the second semiconductor layer.

Abstract: A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g, 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).

Abstract: An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.

Abstract: A topography (40) is provided which includes a device having a transistor formed from a stack of semiconductor layers (42/46). The different semiconductor layers are spaced apart by a gate (60) and by support structures (48) comprising a material having different etch characteristics than the materials of the spaced apart semiconductor layers. The device includes a first transistor channel (76) within the upper semiconductor layer and, in some cases, further includes a second transistor channel within the lower semiconductor layer. The resulting hybrid transistor structure may be fabricated as one of a pair of CMOS transistors, the other of which may include the same configuration or a different configuration. A method for fabricating the hybrid transistor structure includes forming a gate structure surrounding a suspended portion (52) of an upper patterned semiconductor layer (53) and extending down to a surface of a lower semiconductor layer (42).

Abstract: A VCO has a plurality of MIGFETs coupled to provide phase adjustment in response to receiving digital phase adjustment control signals. The VCO includes a ring oscillator implemented as a plurality of serially coupled inverters. A phase adjustment circuit is coupled to the output of each inverter. The phase adjustment circuit of each stage comprises a predetermined number of MIGFETs. In one embodiment, half of the MIGFETs are used to speed-up the phase/frequency of the OUTPUT signal a predetermined amount in response to receiving speed-up control signals. The other half of the MIGFETs are used to slow-down the phase/frequency of the OUTPUT signal a predetermined amount in response to the receiving slow-down control signals. The VCO requires relatively less surface area, is simple, and is easy to implement.

Abstract: A VCO has a plurality of MIGFETs coupled to provide phase adjustment in response to receiving digital phase adjustment control signals. The VCO includes a ring oscillator implemented as a plurality of serially coupled inverters. A phase adjustment circuit is coupled to the output of each inverter. The phase adjustment circuit of each stage comprises a predetermined number of MIGFETs. In one embodiment, half of the MIGFETs are used to speed-up the phase/frequency of the OUTPUT signal a predetermined amount in response to receiving speed-up control signals. The other half of the MIGFETs are used to slow-down the phase/frequency of the OUTPUT signal a predetermined amount in response to the receiving slow-down control signals. The VCO requires relatively less surface area, is simple, and is easy to implement.