Abstract: An AlGaN/GaN HEMT based on fluorinated graphene passivation and a manufacturing method thereof. Monolayer graphene (108) is transferred to an AlGaN (104) surface, is treated by using fluoride ions and then is insulated to thereby replace a conventional nitride passivation layer. Then, a high-k material (109) is grown on the graphene (108), and the high-k material (109) and the graphene (108) are jointly used as a gate dielectric for preparing an AlGaN/GaN metal-insulator-semiconductor (MIS) HEMT. Compared with the traditional passivation structure, the graphene (108) has the advantages of small physical thickness (sub-nanometer scale) and low additional threshold voltage. The structure and the method are simple, the effect is remarkable and the application prospect in technical fields of microelectronics and solid-state electronics is wide.

Abstract: An electronic device that includes a fingerprint recognition circuit and the fingerprint recognition circuit, where the fingerprint recognition circuit includes a protective cover, a fingerprint recognition sensor, a circuit connector, a wall plate, and a lower cover, where the protective cover is located on a top side of the wall plate, the wall plate encircles the fingerprint recognition sensor, the protective cover fully covers an upper opening of the wall plate, electronic waterproof adhesive is provided in a seam between the wall plate and the protective cover, the lower cover is located on a bottom side of the wall plate, the lower cover bonds with a lower part of the wall plate, and the circuit connector is electrically coupled to the fingerprint recognition sensor.

Abstract: An electronic device that includes a fingerprint recognition circuit and the fingerprint recognition circuit, where the fingerprint recognition circuit includes a protective cover, a fingerprint recognition sensor, a circuit connector, a wall plate, and a lower cover, where the protective cover is located on a top side of the wall plate, the wall plate encircles the fingerprint recognition sensor, the protective cover fully covers an upper opening of the wall plate, electronic waterproof adhesive is provided in a seam between the wall plate and the protective cover, the lower cover is located on a bottom side of the wall plate, the lower cover bonds with a lower part of the wall plate, and the circuit connector is electrically coupled to the fingerprint recognition sensor.

Abstract: An AlGaN/GaN HEMT based on fluorinated graphene passivation and a manufacturing method thereof. Monolayer graphene (108) is transferred to an AlGaN (104) surface, is treated by using fluoride ions and then is insulated to thereby replace a conventional nitride passivation layer. Then, a high-k material (109) is grown on the graphene (108), and the high-k material (109) and the graphene (108) are jointly used as a gate dielectric for preparing an AlGaN/GaN metal-insulator-semiconductor (MIS) HEMT. Compared with the traditional passivation structure, the graphene (108) has the advantages of small physical thickness (sub-nanometer scale) and low additional threshold voltage. The structure and the method are simple, the effect is remarkable and the application prospect in technical fields of microelectronics and solid-state electronics is wide.

Abstract: A package for an arcuate planar lightwave circuit (PLC) chip includes a heater plate coupled to a base by a thick and soft support layer. The arcuate PLC is attached to the heater plate by soft adhesive. A hard adhesive is applied to a multi-waveguide end of the arcuate PLC, to additionally strengthen the attachment of the arcuate PLC to the heater plate. The structure allows the mechanical stress due to fiber pull/shock/vibration to be dissipated in the support layer without introducing large wavelength shifts in the arcuate PLC. The support layer also serves as a heat insulator, facilitating uniform heating of the arcuate PLC.

Abstract: A package for an arcuate planar lightwave circuit (PLC) chip includes a heater plate coupled to a base by a thick and soft support layer. The arcuate PLC is attached to the heater plate by soft adhesive. A hard adhesive is applied to a multi-waveguide end of the arcuate PLC, to additionally strengthen the attachment of the arcuate PLC to the heater plate. The structure allows the mechanical stress due to fiber pull/shock/vibration to be dissipated in the support layer without introducing large wavelength shifts in the arcuate PLC. The support layer also serves as a heat insulator, facilitating uniform heating of the arcuate PLC.

Abstract: A package for an arcuate planar lightwave circuit (PLC) chip includes a heater plate coupled to a base by a thick and soft support layer. The arcuate PLC is attached to the heater plate by soft adhesive. A hard adhesive is applied to a multi-waveguide end of the arcuate PLC, to additionally strengthen the attachment of the arcuate PLC to the heater plate. The structure allows the mechanical stress due to fiber pull/shock/vibration to be dissipated in the support layer without introducing large wavelength shifts in the arcuate PLC. The support layer also serves as a heat insulator, facilitating uniform heating of the arcuate PLC.

Abstract: A package for an arcuate planar lightwave circuit (PLC) chip includes a heater plate coupled to a base by a thick and soft support layer. The arcuate PLC is attached to the heater plate by soft adhesive. A hard adhesive is applied to a multi-waveguide end of the arcuate PLC, to additionally strengthen the attachment of the arcuate PLC to the heater plate. The structure allows the mechanical stress due to fiber pull/shock/vibration to be dissipated in the support layer without introducing large wavelength shifts in the arcuate PLC. The support layer also serves as a heat insulator, facilitating uniform heating of the arcuate PLC.

Abstract: The invention relates to an electro-static variable optical attenuator suitable for use in a small form factor pluggable module. A short cladding suppressing fiber, such as a double clad optical fiber, dissipates attenuated light coupled to the cladding to reduce modal interference in the output light, while also reducing PDL and WDL introduced by the off set attenuation mechanism.

Abstract: The invention relates to an electro-static variable optical attenuator suitable for use in a small form factor pluggable module. A short cladding suppressing fiber, such as a double clad optical fiber, dissipates attenuated light coupled to the cladding to reduce modal interference in the output light, while also reducing PDL and WDL introduced by the off set attenuation mechanism.

Abstract: The present invention relates to a manufacturing method of SOI devices, and in particular, to a manufacturing method of SOI high-voltage power devices.

Abstract: A method of manufacturing a SOI high voltage power chip with trenches is disclosed. The method comprises: forming a cave and trenches at a SOI substrate; filling oxide in the cave; oxidizing the trenches, forming oxide isolation regions for separating low voltage devices at the same time; filling oxide in the oxidized trenches; and then forming drain regions, source regions and gate regions for a high voltage power device and low voltage devices. The process involves depositing an oxide layer overlapping the cave of the SOI substrate. A SOI high voltage power chip thus made will withstand at least above 700V voltage.

Abstract: The present invention relates to a method of fabricating an SOI SJ LDMOS structure that can completely eliminate the substrate-assisted depletion effects, comprising the following steps: step one: a conducting layer is prepared below the SOI BOX layer using the bonding technique; the conducting layer is prepared in the following way: depositing a barrier layer on a first bulk silicon wafer, and then depositing a charge conducting layer, thereby obtaining a first intermediate structure; forming a silicon dioxide layer on a second bulk silicon wafer via thermal oxidation, then depositing a barrier layer, and finally depositing a charge conducting layer, thereby obtaining a second intermediate structure; bonding the first intermediate structure and the second intermediate structure using the metal bonding technology to arrange the conducting layer below the SOI BOX layer; step two: a SJ LDMOS structure is fabricated on the SOI substrate having a conducting layer.

Abstract: The present invention provides a method of fabricating a graphene-based field effect transistor, which includes steps of: providing a semiconductor substrate on which a non-functionized graphene layer is formed; forming a metal oxide film as a nucleation layer through a reaction between a metal source and water which acts as oxidizer and is physically absorbed to a surface of the graphene layer; and generating a HfO2 gate dielectric layer through a reaction between a hafnium source and water acting as oxidizer by using the nucealtion layer. In comparison with the prior art, the method of the present invention is mainly characterized in that the metal oxide film acting as the nucleation layer is formed through a reaction between the metal source and water which acts as oxidizer and is physically absorbed to the surface of graphene.

Abstract: The present invention relates to a method of depositing a gate dielectric, a method of preparing a MIS capacitor and the MIS capacitor. In the method of depositing the gate dielectric, a semiconductor substrate surface is preprocessed with oxygen plasma and nitrogen-containing plasma to form a nitrogen-containing oxide layer thereon. Then, a high-k gate dielectric layer is grown on the nitrogen-containing oxide layer surface by a plasma-enhanced atomic layer deposition process, and the oxide layer converts during the gate dielectric layer growth process into a buffer layer of a dielectric constant higher than SiO2. Then, a metal electrode is formed on both an upper layer and a lower layer of the thus-formed semiconductor construction, so that a MIS capacitor is prepared.

Abstract: The present invention relates to a method of fabricating an SOI SJ LDMOS structure that can completely eliminate the substrate-assisted depletion effects, comprising the following steps: step one: a conducting layer is prepared below the SOI BOX layer using the bonding technique; the conducting layer is prepared in the following way: depositing a barrier layer on a first bulk silicon wafer, and then depositing a charge conducting layer, thereby obtaining a first intermediate structure; forming a silicon dioxide layer on a second bulk silicon wafer via thermal oxidation, then depositing a barrier layer, and finally depositing a charge conducting layer, thereby obtaining a second intermediate structure; bonding the first intermediate structure and the second intermediate structure using the metal bonding technology to arrange the conducting layer below the SOI BOX layer; step two: a SJ LDMOS structure is fabricated on the SOI substrate having a conducting layer.

Abstract: The present invention relates to a manufacturing method of SOI devices, and in particular, to a manufacturing method of SOI high-voltage power devices.

Abstract: A method of manufacturing a SOI high voltage power chip with trenches is disclosed. The method comprises: forming a cave and trenches at a SOI substrate; filling oxide in the cave; oxidizing the trenches, forming oxide isolation regions for separating low voltage devices at the same time; filling oxide in the oxidized trenches; and then forming drain regions, source regions and gate regions for a high voltage power device and low voltage devices. The process involves depositing an oxide layer overlapping the cave of the SOI substrate. A SOI high voltage power chip thus made will withstand at least above 700V voltage.

Abstract: The present invention discloses an SOI CMOS device having a vertical gate structure, comprising: an SOI substrate, and an NMOS region and a PMOS region grown on the SOI substrate, wherein the NMOS region and the PMOS region share one vertical gate region, said vertical gate region lying in the same plane as the NMOS region and the PMOS region and between the NMOS region and the PMOS region; a gate oxide layer is arranged between the vertical gate region and the NMOS region for isolation; and a gate oxide layer is arranged between the vertical gate region and the PMOS region for isolation. The present invention occupies small area, contains less pattern layers, requires a simple process, has an open body region that can completely avoid the floating effect of the traditional SOI CMOS device, and is convenient to parasitic resistance and capacitance tests.