Abstract: The present invention relates to a ventilating and blanking device for a coal storage Eurosilo. The ventilating and blanking device includes a top blanking pipe, an axial flow fan and a baffle door, the top blanking pipe including a first pipeline and a second pipeline, an air supply pipe is connected to a side wall of the second pipeline, and the baffle door is connected to a driving mechanism; during blanking, the driving mechanism drives the baffle door so as to make the baffle door close the air supply pipe and the axial flow fan is shut off; and during ventilation, the driving mechanism drives the baffle door so as to make the baffle door close the first pipeline, and the axial flow fan is turned on. Compared with the prior art, the present invention has the advantages of ventilation efficiency, good ventilation effect, etc.

Abstract: A preparation method of a high-thermal-conductivity and net-size silicon nitride ceramic substrate includes the following steps: (1) mixing an original powder, a sintering aid, a dispersant, a defoamer, a binder, and a plasticizer in a protective atmosphere to allow vacuum degassing to obtain a mixed slurry; (2) subjecting the mixed slurry to tape casting and drying in a nitrogen atmosphere to obtain a first green body; (3) subjecting the first green body to shaping pretreatment to obtain a second green body; (4) subjecting the second green body to debonding at 500° C. to 900° C. to obtain a third green body; and (5) subjecting the third green body to gas pressure sintering in a nitrogen atmosphere at 1,800° C. to 2,000° C. to obtain the high-thermal-conductivity and net-size silicon nitride ceramic substrate.

Abstract: The semiconductor structure manufacturing method includes the steps of: providing a substrate with bit line contact regions and isolation regions located between adjacent bit line contact regions; forming a groove in the substrate, the bottom of the groove exposes the bit line contact region and the isolation region adjacent to the bit line contact region; forming a contact region isolation layer covering at least sidewalls of the groove; and forming a contact region to cover the contact region isolating the surface of the layer and filling the bit line contact layer of the groove, the bit line contact layer being in contact with the bit line contact region at the bottom of the groove; forming a bit line layer on the bit line contact layer. The invention avoids damage to the sidewalls of the active region in the substrate.

Abstract: A method for manufacturing a semiconductor structure and the semiconductor structure are provided. The method includes the following operations. A substrate provided with a plurality of active areas arranged at intervals is provided. A first laminated structure and a first photoresist layer are sequentially formed on the substrate. Negative Type Develop (NTD) is performed on the first photoresist layer, to form a first pattern. The first laminated structure is etched along the first pattern, to form a second pattern in the first laminated structure. The substrate is etched up to a preset depth by taking the first laminated structure having the second pattern as a mask, to form a recess and form a plurality of protuberances arranged at intervals on the reserved substrate. The recess surrounds the protuberance, and the active area is exposed between the protuberances.

Abstract: The present application discloses a semiconductor structure and a method for fabrication. This technique improves the stability of the bit line structure. The semiconductor structure is formed in a bit line trench in a substrate, it includes: a bit line conductive layer formed in the bit line trench, and the top surface of the bit line conductive layer is higher the top surface of the substrate; a barrier layer formed at least partially between the bit line conductive layer and the inner wall of the bit line trench; and an isolation layer formed on top of the bit line conductive layer.

Abstract: The present application relates to a semiconductor structure and a method of manufacturing the same. The method includes: providing a substrate; forming a bitline contact hole located in the substrate, and a non-metal conductive layer with which a surface of the substrate is covered and the bitline contact hole is filled, the non-metal conductive layer provided with a first opening therein, the first opening aligned with the bitline contact hole; forming a metal conductive layer, with which a surface of the non-metal conductive layer is covered; forming an insulation layer, with which a surface of the metal conductive layer surface is covered; and etching the insulation layer, the metal conductive layer, and the non-metal conductive layer to form a bitline structure.

Abstract: The present disclosure relates to a method for preparing a silicon nitride ceramic material. The method including: (1) with at least one of silicon powder and silicon nitride powder as original powder and Y2O3 powder and MgO powder as sintering aids, the original powder and the sintering aids are mixed in a protective atmosphere, and the mixture is formed into a green body; (2) the resulting green body is put into a reducing atmosphere and pretreated at 500° C. to 800° C. to obtain a biscuit; and the reducing atmosphere is a hydrogen/nitrogen mixed atmosphere with a hydrogen content not higher than 5%; (3) the resulting biscuit is put into a nitrogen atmosphere and subjected to low-temperature heat treatment at 1600° C. to 1800° C. and high-temperature heat treatment at 1800° C. to 2000° C. in sequence.

Abstract: A preparation method for a copper plate-covered silicon nitride ceramic substrate is provided. The structure of the copper plate-covered silicon nitride ceramic substrate includes a silicon nitride ceramic substrate, copper sheets disposed on the upper and lower sides of the silicon nitride ceramic substrate and soldering layers disposed between the copper sheets and the silicon nitride ceramic substrate; the composition of the silicon nitride ceramic substrate comprises a silicon nitride phase (more than or equal to 95 wt %); and a grain boundary phase (containing at least three elements (Y, Mg and O) and less than or equal to 5 wt %, and the content of a crystalline phase in the grain boundary phase is more than or equal to 40 vol %); and the sintering aids are Y2O3 and MgO. The two-step sintering process comprises: in a nitrogen atmosphere, performing low-temperature heat treatment and high-temperature heat treatment in sequence.

Abstract: The present disclosure relates to a batch sintering method for a high-property silicon nitride ceramic substrate. The batch sintering method includes: (1) silicon nitride ceramic substrate green bodies are stacked and put into a boron nitride crucible, and a layer of boron nitride powder is applied between adjacent silicon nitride ceramic substrate green bodies; (2) after step-by-step vacuumization, debinding is performed in a nitrogen atmosphere or a reducing atmosphere at 500° C. to 900° C.; (3) gas pressure sintering is then performed in a nitrogen atmosphere at 1800° C. to 2000° C., completing the batch preparation of the high-property silicon nitride ceramic substrate.

Abstract: A preparation method for a semiconductor structure and a semiconductor structure are provided. Herein, the preparation method comprises: providing a structure to be processed, wherein the structure to be processed comprises a substrate, and an etching target layer, a bottom mask layer and a first mask layer stacked on the substrate; patterning the first mask layer to form a first pattern, the first pattern exposing parts of the bottom mask layer; forming spacers with vertical sidewall morphology on sidewalls of the first mask layer; removing the first mask layer; filling a gap between the spacers with a filling layer, in which a material of the spacers to a material of the filling layer has a high etching selectivity ratio; and removing the spacers.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, a first mask and a second mask, etching the substrate by respectively using the first mask and the second mask, so as to form first grooves and second grooves on the substrate, wherein regions, in the substrate, where the first grooves and the second grooves are located form bit line grooves; and forming a conductive layer in each of the bit line grooves.

Abstract: A method includes the following operations for preparing a semiconductor structure, a semiconductor, and a semiconductor memory. A first dielectric layer and a first barrier layer are deposited on a substrate including an active area in sequence. A first mask including a first etching pattern is formed on the first barrier layer, and includes a groove extending in a first direction and uniformly distributed etching holes. Herein, the groove penetrates through the etching hole, and the depth of the etching hole is larger than that of the groove. Etching is performed along the first etching pattern, to remove the first barrier layer and etch the first dielectric layer to form a conductive channel.

Abstract: A memory device and a method for manufacturing a memory device are provided. The memory device includes: a substrate, and a plurality of first capacitors embedded in the substrate; a plurality of first vertical transistors and a plurality of second vertical transistors, in which the plurality of first vertical transistors and the plurality of second vertical transistors are arranged on the substrate, and in which each of the plurality of first vertical transistors is electrically connected to a respective one of the plurality of first capacitors; and a plurality of second capacitors arranged on the plurality of first vertical transistors and the plurality of second vertical transistors, in which each of the plurality of second capacitors is electrically connected to a respective one of the plurality of second vertical transistors.

Abstract: Provided is a semiconductor structure and a method for manufacturing the same. The method includes forming a spin on hard mask layer on a base, active areas arranged at intervals in the base, bit lines arranged at intervals and extending in a first direction on the base, each bit line electrically connected to at least one active area, and the spin on hard mask layer filled between the bit lines and covering the bit lines; removing part of the spin on hard mask layer to form first trenches arranged at intervals and extending in a second direction; forming first sacrificial layers in the first trenches; removing the spin on hard mask layer between the first sacrificial layers to form second trenches; forming first supporting layers in the second trenches; removing the first sacrificial layers and elongating the first trenches located between adjacent bit lines to the active areas.

Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate including a memory area and a peripheral area; forming an insulating layer on a surface of the memory area, and forming a first metal layer on a surface of the peripheral area; etching the insulating layer and the memory area of the semiconductor substrate to form a plurality of bit line trenches arranged at intervals along a first direction and etched insulating layer, in which part of the bit line trench is located in the memory area of the semiconductor substrate, and the other part of the bit line trench is located in the etched insulating layer; forming a second metal layer on surfaces of the bit line trench, the memory area and the first metal layer; and etching the first metal layer and the second metal layer to form a semi-buried bit line structure and peripheral gate.

Abstract: An embodiment provides a method for fabricating a semiconductor structure. The method includes: providing a semiconductor substrate having an active area, the active area including a first active area and a second active area isolated from each other; forming a bitline contact groove on the semiconductor substrate, the bitline contact groove exposing the first active area; forming an etch stop layer covering a sidewall of the bitline contact groove, the etch stop layer exposing a partial area of the first active area at a bottom of the bitline contact groove; etching the semiconductor substrate by using the etch stop layer as a mask to form a pit at the bottom of the bitline contact groove, the pit being at least partially positioned in the first active area; removing the etch stop layer; forming a bitline structure; and forming a conductive plug electrically connected to the second active area.

Abstract: The semiconductor structure manufacturing method includes the steps of: providing a substrate with bit line contact regions and isolation regions located between adjacent bit line contact regions; forming a groove in the substrate, the bottom of the groove exposes the bit line contact region and the isolation region adjacent to the bit line contact region; forming a contact region isolation layer covering at least sidewalls of the groove; and forming a contact region to cover the contact region isolating the surface of the layer and filling the bit line contact layer of the groove, the bit line contact layer being in contact with the bit line contact region at the bottom of the groove; forming a bit line layer on the bit line contact layer. The invention avoids damage to the sidewalls of the active region in the substrate.

Abstract: A semiconductor structure and the method for forming the same are provided. The method includes: providing a substrate including an active region; forming a word line in the substrate including a first portion and a second portion located at the end of the first portion, wherein the second portion of the word line protrudes from the first portion of the word line along the direction perpendicular to the substrate; forming a dielectric layer covering the substrate; and etching the dielectric layer and a part of the substrate to simultaneously form a first contact hole exposing the second portion of the word line and a second contact hole exposing the active region. The invention reduces the etching time and improves the etching efficiency. It avoids an excessively large etching depth of the second contact hole, thereby reducing the damage to the active region and the leakage current inside the semiconductor structure.

Abstract: The present disclosure provides a memory device, and a semiconductor structure and a forming method thereof, which includes: providing a substrate, which includes a plurality of bit line structures, forming a cover layer on each of the bit line structures, forming a first insulating layer and a second insulating layer sequentially on a side wall of each cover layer, and filling a space between second insulating layers of two adjacent bit line structures with a conductive contact layer; tops of the conductive contact layers and the second insulating layers are all lower than surfaces of the cover layers and higher than surfaces of the bit line structures; tops of the first insulating layers are flush with those of the conductive contact layers and the second insulating layers; and etching back the conductive contact layers, to form a capacitor contact hole between cover layers of two adjacent bit line structures.

Abstract: Embodiments provide a method for fabricating a memory and a memory. This method includes: providing a substrate, the substrate being internally provided with a plurality of active areas, and each of the plurality of active areas including a first contact region and a second contact region; forming a plurality of bit lines on the substrate, each of the plurality of bit lines being connected to at least one of the first contact regions; forming an isolation layer on each of the plurality of bit lines, the isolation layer covering each of the plurality of bit lines and the substrate, the isolation layer being further provided with a plurality of filling holes corresponding to the plurality of second contact regions one to one; etching the isolation layer and the substrate along the plurality of filling holes, to fill in the plurality of second contact regions.