Abstract: A method of manufacturing a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, first and second fins on the semiconductor substrate and separated by a trench. The first fin includes a first portion having a first conductivity type and a second portion having a second conductivity type different from the first conductivity type, the first and second portions are adjacent to each other, and the second portion connected to the second fin through the semiconductor substrate. The semiconductor device also includes a gate structure on the first and second portions and including a gate insulator layer on the first and second portions, a gate on a portion of the gate insulator layer on the first portion, and a dummy gate on the second portion and including an insulating layer or an undoped semiconductor layer and adjacent to the gate.

Abstract: This disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device may include a substrate; a first fin on the substrate for forming a first electronic component; a first gate structure on a portion of the first fin including a first gate dielectric layer on a portion of the first fin and a first gate on the first gate dielectric layer; and a first source region and a first drain region that each at one of two sides of the first gate structure and at least partially located in the first fin, where the first gate dielectric layer comprises a first region abutting against the first drain region, a second region abutting against the first source region, and a third region between the first region and the second region, and wherein thickness of the first region is greater than that of the third region.

Abstract: A method of manufacturing a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, first and second fins on the semiconductor substrate and separated by a trench. The first fin includes a first portion having a first conductivity type and a second portion having a second conductivity type different from the first conductivity type, the first and second portions are adjacent to each other, and the second portion connected to the second fin through the semiconductor substrate. The semiconductor device also includes a gate structure on the first and second portions and including a gate insulator layer on the first and second portions, a gate on a portion of the gate insulator layer on the first portion, and a dummy gate on the second portion and including an insulating layer or an undoped semiconductor layer and adjacent to the gate.

Abstract: A method of manufacturing a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, first and second fins on the semiconductor substrate and separated by a trench. The first fin includes a first portion having a first conductivity type and a second portion having a second conductivity type different from the first conductivity type, the first and second portions are adjacent to each other, and the second portion connected to the second fin through the semiconductor substrate. The semiconductor device also includes a gate structure on the first and second portions and including a gate insulator layer on the first and second portions, a gate on a portion of the gate insulator layer on the first portion, and a dummy gate on the second portion and including an insulating layer or an undoped semiconductor layer and adjacent to the gate.

Abstract: This disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device may include a substrate; a first fin on the substrate for forming a first electronic component; a first gate structure on a portion of the first fin including a first gate dielectric layer on a portion of the first fin and a first gate on the first gate dielectric layer; and a first source region and a first drain region that each at one of two sides of the first gate structure and at least partially located in the first fin, where the first gate dielectric layer comprises a first region abutting against the first drain region, a second region abutting against the first source region, and a third region between the first region and the second region, and wherein thickness of the first region is greater than that of the third region.

Abstract: An integrated device includes a field effect transistor formed within and upon an active region of a substrate and a resistor formed on an isolation region of the substrate. The field effect transistor includes a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer arranged in order from bottom to top. The resistor includes a resistor body being an enclosure portion of the first conductive layer and resistor terminals being portions of the second conductive layer on distal ends of the resistor body. A method for manufacturing a semiconductor device includes forming a gate stacked structure and a resistor stacked structure at the same time by patterning a dielectric layer, a first conductive layer and a second conductive layer. The method also includes forming a resistor having a resistor body by patterning the resistor stacked structure.

Abstract: A method for fabricating a semiconductor structure includes providing a substrate, forming an interface layer on the substrate, and then performing a first annealing process on the interface layer under a nitrogen-containing environment to form a nitrogen-containing layer from a top portion of the interface layer. The first annealing process also deactivates non-bonded silicon ions and oxygen ions in the interface layer. The method further includes forming a high-k dielectric layer on the nitrogen-containing layer, and performing a second annealing process on the high-k dielectric layer to allow nitrogen ions in the nitrogen-containing layer to diffuse into the high-k dielectric layer to reduce a density of active oxygen vacancies in the high-k dielectric layer. Finally, the method includes forming a gate electrode layer on the high-k dielectric layer.

Abstract: An integrated device includes a field effect transistor formed within and upon, an active region of a substrate and a resistor formed on an isolation region of the substrate. The field effect transistor includes a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer arranged in order from bottom to top. The resistor includes a resistor body being an enclosure portion of the first conductive layer and resistor terminals being portions of the second conductive layer on distal ends of the resistor body. A method for manufacturing a semiconductor device includes forming a gate stacked structure and a resistor stacked structure at the same time by patterning a dielectric layer, a first conductive layer and a second conductive layer. The method also includes forming a resistor having a resistor body by patterning the resistor stacked structure.

Abstract: A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region.

Abstract: A method of manufacturing a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, first and second fins on the semiconductor substrate and separated by a trench. The first fin includes a first portion having a first conductivity type and a second portion having a second conductivity type different from the first conductivity type, the first and second portions are adjacent to each other, and the second portion connected to the second fin through the semiconductor substrate. The semiconductor device also includes a gate structure on the first and second portions and including a gate insulator layer on the first and second portions, a gate on a portion of the gate insulator layer on the first portion, and a dummy gate on the second portion and including an insulating layer or an undoped semiconductor layer and adjacent to the gate.

Abstract: The present disclosure provides semiconductor devices and fabrication methods thereof. A stacked substrate includes an insulating layer between a substrate and a semiconductor layer. First openings are formed in the semiconductor layer to define a first distance between adjacent sidewalls of adjacent first openings. Spacers are formed on sidewall surfaces of each first opening. Second openings corresponding to the first openings are formed through the insulating layer and into the substrate. The sidewall surfaces of the substrate in the second openings are etched to define a second distance between adjacent substrate sidewalls of adjacent etched second openings. The second distance is shorter than the first distance. An isolation layer is formed in the first and second openings. Conductive structures are formed on the semiconductor layer on both sides of a gate structure formed on the semiconductor layer. The conductive structures penetrate through the isolation layer and into the substrate.

Abstract: A semiconductor device includes a plurality of substantially vertical semiconductor pillars on a substrate, and a hard mask layer overlying the plurality of semiconductor pillars. A contiguous portion of the hard mask layer connects two or more of the plurality of semiconductor pillars.

Abstract: An integrated device includes a field effect transistor formed within and upon an active region of a substrate and a resistor formed on an isolation region of the substrate. The field effect transistor includes a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer arranged in order from bottom to top. The resistor includes a resistor body being an enclosure portion of the first conductive layer and resistor terminals being portions of the second conductive layer on distal ends of the resistor body. A method for manufacturing a semiconductor device includes forming a gate stacked structure and a resistor stacked structure at the same time by patterning a dielectric layer, a first conductive layer and a second conductive layer. The method also includes forming a resistor having a resistor body by patterning the resistor stacked structure.

Abstract: An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and having a first lattice structure and a first grain size, wherein the first thickness is greater than the first grain size; and performing an annealing process to change the first lattice structure of the conductive film to a second lattice structure and to change the first grain size to a second grain size. The second grain size is greater than the first grain size, and the first thickness is greater than or equal to the second grain size. The method also includes etching portion of the conductive film to form at least one conductive layer; etching portion of the conductive layer to form at least one trench having a depth smaller than the first thickness in the conductive layer to form an electrical interconnection wire and conductive vias; and forming a dielectric layer covering the substrate, sidewalls of the conductive layer, and the trench.

Abstract: The present disclosure provides semiconductor devices and fabrication methods thereof. A stacked substrate includes an insulating layer between a substrate and a semiconductor layer. First openings are formed in the semiconductor layer to define a first distance between adjacent sidewalls of adjacent first openings. Spacers are formed on sidewall surfaces of each first opening. Second openings corresponding to the first openings are formed through the insulating layer and into the substrate. The sidewall surfaces of the substrate in the second openings are etched to define a second distance between adjacent substrate sidewalls of adjacent etched second openings. The second distance is shorter than the first distance. An isolation layer is formed in the first and second openings. Conductive structures are formed on the semiconductor layer on both sides of a gate structure formed on the semiconductor layer. The conductive structures penetrate through the isolation layer and into the substrate.

Abstract: A MEMS capacitive pressure sensor is provided. The MEMS capacitive pressure sensor includes a substrate having a first region and a second region, and a first dielectric layer formed on the substrate. The capacitive pressure sensor also includes a second dielectric layer having a step surface profile formed on the first dielectric layer, and a first electrode layer having a step surface profile formed on the second dielectric layer. Further, the MEMS capacitive pressure sensor includes an insulation layer formed on the first electrode layer, and a second electrode layer having a step surface profile with a portion formed on the insulation layer in the peripheral region and the rest suspended over the first electrode layer in the device region. Further, the MEMS capacitive pressure sensor also includes a chamber having a step surface profile formed between the first electrode layer and the second electrode layer.

Abstract: A multiple patterning method is provided. The multiple patterning method includes providing a substrate; and forming a sacrificial film on the substrate. The multiple patterning method also includes forming a first mask film on the sacrificial film; and forming a second mask film for subsequently forming a certain structure to protect the subsequently formed mask structures on the first mask film. Further, the multiple patterning method includes forming first mask structures and second mask structures by etching the second mask film, the first mask film, and the sacrificial film.

Abstract: A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate; and a plurality of parallel first conductive layers formed on the substrate. The semiconductor structure also includes a composite magnetic structure having a plurality of magnetic layers and a plurality of insulation layers with a sandwich arrangement formed on a portion of the substrate and portions of surfaces of the plurality of first conductive layers. Further, the semiconductor structure includes a plurality of first conductive vias and a plurality of second conductive vias formed on the first conductive layers at both sides of the composite magnetic structure. Further, the semiconductor structure also includes a plurality of second conductive layers formed on a top surface of the composite magnetic structure, top surfaces of the first conductive vias, and top surfaces of the second conductive vias to form at least one coil structure wrapping around the composite magnetic structure.

Abstract: A method for fabricating a semiconductor structure includes providing a substrate, forming an interface layer on the substrate, and then performing a first annealing process on the interface layer under a nitrogen-containing environment to form a nitrogen-containing layer from a top portion of the interface layer. The first annealing process also deactivates non-bonded silicon ions and oxygen ions in the interface layer. The method further includes forming a high-k dielectric layer on the nitrogen-containing layer, and performing a second annealing process on the high-k dielectric layer to allow nitrogen ions in the nitrogen-containing layer to diffuse into the high-k dielectric layer to reduce a density of active oxygen vacancies in the high-k dielectric layer. Finally, the method includes forming a gate electrode layer on the high-k dielectric layer.