Abstract: One or more shader processor inputs (SPIs) provide work items from a thread group for execution on one or more shader engines. A command processor selectively dispatches the work items to the SPIs based on a size of the thread group and a format of cache lines of a cache implemented in the one or more shader engines. The command processor operates in a tile mode in which the command processor schedules the work items in multidimensional blocks that correspond to the format of the cache lines. In some cases, the format of the cache lines is determined by a texture surface format and a swizzle mode for storing texture data. The SPIs (or corresponding drivers) adaptively select wave size, tile size, and wave walk mode based on thread group size, UAV surface format. The SPIs adaptively launch and schedule waves in a thread group based on selected file size, wave walk mode, and wave size to improve cache locality, reduce memory access, and create address pattern to improve memory efficiency.

Abstract: One or more shader processor inputs (SPIs) provide work items from a thread group for execution on one or more shader engines. A command processor selectively dispatches the work items to the SPIs based on a size of the thread group and a format of cache lines of a cache implemented in the one or more shader engines. The command processor operates in a tile mode in which the command processor schedules the work items in multidimensional blocks that correspond to the format of the cache lines. In some cases, the format of the cache lines is determined by a texture surface format and a swizzle mode for storing texture data. The SPIs (or corresponding drivers) adaptively select wave size, tile size, and wave walk mode based on thread group size, UAV surface format. The SPIs adaptively launch and schedule waves in a thread group based on selected tile size, wave walk mode, and wave size to improve cache locality, reduce memory access, and create address pattern to improve memory efficiency.

Abstract: A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.

Abstract: A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.

Abstract: A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.

Abstract: A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.