Abstract: A memory device can include multiple memory cells and a processing device operatively coupled with the memory device to perform operations including grouping the memory cells into a groups based on a metric reflecting an electrical distance of a memory cell from a voltage source, and determining, for each group, a respective share of write operations, wherein the share of write operations is related to an aggregate value of the metric for memory cells of the group. The operations can also include distributing the write operations to each group according to the share of write operations determined for the group.

Abstract: Systems, methods, and apparatus to select an enhanced write pulse for a write operation in a memory device. In one approach, stronger reset pulses are triggered when there is an increased risk of memory cell threshold voltage degradation. Memory cells read by a relatively higher number of read operations are recorded by a controller of a memory device by updating a lookup table with addresses of the memory cells read. For a new write operation, the controller determines if a reset on set write operation is to be performed. The controller also searches the lookup table to determine if an address for the target bits or codeword of the write operation are in the lookup table. If both conditions are satisfied, then the magnitude of the write pulse is increased for programming the memory cells.

Abstract: Disclosed are techniques for correcting drift accumulation in memory cells. In some aspects, the techniques described herein relate to a memory device including: a memory array, the memory array including a set of memory cells; and a memory controller configured to read data from the memory array, the memory controller configured to: sense a first distribution of the set of memory cells, detect a missing cell in the first distribution, increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution, detect that a second memory cell in a second distribution was read while sensing the first distribution, and mask the second memory cell and mark the second memory cell as belonging to the second distribution.

Abstract: A processing method and a processing device for saving energy of a base station are provided. The method includes: obtaining engineering parameter data and MR data of a base station; gridding the MR data to obtain grid MR data, and calculating a calculated value of longitude and latitude data of the base station according to the grid MR data; comparing the calculated value of the longitude and latitude data of the base station with longitude and latitude data of the base station in the engineering parameter data to select engineering parameter data, which is input into a load prediction model, of the base station; inputting the engineering parameter data of the base station selected into the load prediction model to train and predict the load prediction model; and issuing a corresponding power-saving turn-off strategy according to a prediction result of the load prediction model.

Abstract: A memory device can include multiple memory cells and a processing device operatively coupled with the memory device to perform operations including grouping the memory cells into a groups based on a metric reflecting an electrical distance of a memory cell from a voltage source, and determining, for each group, a respective share of write operations, wherein the share of write operations is related to an aggregate value of the metric for memory cells of the group. The operations can also include distributing the write operations to each group according to the share of write operations determined for the group.

Abstract: Bake temperatures for memory blocks can be determined as part of an operation to allocate memory blocks for us by a memory device. If a temperature of a particular memory block among the plurality of memory blocks meets or exceeds a threshold operational temperature corresponding to a memory device containing the plurality of memory blocks, the particular memory block can be allocated for receipt and/or storage of data.

Abstract: The present disclosure includes apparatuses, methods, and systems for predicting and compensating for degradation of memory cells. An embodiment includes a memory having a group of memory cells, and circuitry configured to, upon a quantity of sense operations performed on the group of memory cells meeting or exceeding a threshold quantity, perform a sense operation on the group of memory cells using a positive sensing voltage and perform a sense operation on the group of memory cells using a negative sensing voltage, and perform an operation to program the memory cells of the group determined to be in a reset data state by both of the sense operations to the reset data state.

Abstract: Systems, methods, and apparatus to evaluate read margin when reading memory cells in a memory device. In one approach, a controller of a memory device applies an initial read voltage of an initial polarity to memory cells. Errors from the read are used to determine whether read retry is needed. If so, a pre-read voltage of an opposite polarity is applied, and errors determined. Based on the errors from applying the pre-read voltage, a polarity is selected for the read retry voltage. The read retry voltage of the selected polarity is then applied to the memory cells.

Abstract: Various embodiments enable read buffering in connection with data block transfer on a memory device. For some embodiments, read buffering from a set of cache blocks is enabled during a period of wait time after data is copied (e.g., data is transferred, such as part of a compaction operation) from the set of cache blocks to a set of non-cache blocks. In various embodiments, after the wait time, data stored on the set of cache blocks is erased (e.g., the set of cache blocks is released) and read buffering from the set of cache blocks is disabled.

Abstract: Apparatuses, methods, and systems for generating patterns for memory using threshold voltage difference are disclosed. An embodiment includes circuitry and a memory array including a plurality of memory cells. The circuitry can select a group of memory cells from the plurality of memory cells, program each memory cell of the group to a first data state, determine a first threshold voltage of each memory cell of the group, program each memory cell of the group to a second data state, perform a number of snapback events on each memory cell of the group, program each memory cell of the group to the first data state, determine a second threshold voltage of each memory cell of the group having the first data state, and generate a pattern for the memory array based, at least in part, on a difference between the first threshold voltage and the second threshold voltage.

Abstract: The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to apply, prior to sensing a data state of a memory cell of the plurality of memory cells, a voltage to an access line to which the memory cell is coupled, determine whether an amount of current on the access line in response to the applied voltage meets or exceeds a threshold amount of current, and determine whether to increase a magnitude of a current used to sense the data state of the memory cell based on whether the amount of current on the access line in response to the applied voltage meets or exceeds the threshold amount of current.

Abstract: Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.

Abstract: The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to count a number of program operations performed on the memory cells of the memory during operation of the memory, and increase a magnitude of a current used to sense a data state of the memory cells of the memory upon the count of the number of program operations reaching a threshold count.

Abstract: Systems, methods, and apparatus to evaluate read margin when reading memory cells in a memory device. In one approach, a controller of a memory device applies an initial read voltage of an initial polarity to memory cells. Errors from the read are used to determine whether read retry is needed. If so, a pre-read voltage of an opposite polarity is applied, and errors determined. Based on the errors from applying the pre-read voltage, a polarity is selected for the read retry voltage. The read retry voltage of the selected polarity is then applied to the memory cells.

Abstract: A memory device can include multiple memory cells and a processing device operatively coupled with the memory device to perform operations including grouping the memory cells into a groups based on a metric reflecting an electrical distance of a memory cell from a voltage source, and determining, for each group, a respective share of write operations, wherein the share of write operations is related to an aggregate value of the metric for memory cells of the group. The operations can also include distributing the write operations to each group according to the share of write operations determined for the group.

Abstract: The present disclosure includes systems, apparatuses, and methods related to generating a random data value. For example, a first read operation may be performed on a memory cell programmed to a first state, wherein the first read operation is performed using a first read voltage that is within a predetermined threshold voltage distribution corresponding to the first state. A programming signal may be applied to the memory cell responsive to the first read operation resulting in a snapback event, wherein the programming signal is configured to place the memory cell in a second state. A second read operation may be performed to determine whether the memory cell is in the first state or the second state using a second read voltage that is between the predetermined threshold voltage distribution corresponding to the first state and a second threshold voltage distribution corresponding to the second state.

Abstract: Methods and systems include memory devices with multiple memory cells configured to store data. The memory devices also include a cache configured to store at least a portion of the data to provide access to the at least the portion of the data without accessing the multiple memory cells. The memory devices also include control circuitry configured to receive a read command having a target address. Based on the target address, the control circuitry is configured to determine that the at least the portion of the data is present in the cache. Using the cache, the control circuitry also outputs read data from the cache without accessing the plurality of memory cells.

Abstract: The present disclosure includes apparatuses, methods, and systems for predicting and compensating for degradation of memory cells. An embodiment includes a memory having a group of memory cells, and circuitry configured to, upon a quantity of sense operations performed on the group of memory cells meeting or exceeding a threshold quantity, perform a sense operation on the group of memory cells using a positive sensing voltage and perform a sense operation on the group of memory cells using a negative sensing voltage, and perform an operation to program the memory cells of the group determined to be in a reset data state by both of the sense operations to the reset data state.

Abstract: The present disclosure includes systems, apparatuses, and methods related to generating a random data value. For example, a first read operation may be performed on a memory cell programmed to a first state, wherein the first read operation is performed using a first read voltage that is within a predetermined threshold voltage distribution corresponding to the first state. A programming signal may be applied to the memory cell responsive to the first read operation resulting in a snapback event, wherein the programming signal is configured to place the memory cell in a second state. A second read operation may be performed to determine whether the memory cell is in the first state or the second state using a second read voltage that is between the predetermined threshold voltage distribution corresponding to the first state and a second threshold voltage distribution corresponding to the second state.

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.