Patents by Inventor Zhongyuan Lu

Zhongyuan Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12131778
    Abstract: Systems, methods, and apparatus to select an enhanced write pulse for a write operation in a memory device. In one approach, stronger reset pulses are triggered when there is an increased risk of memory cell threshold voltage degradation. Memory cells read by a relatively higher number of read operations are recorded by a controller of a memory device by updating a lookup table with addresses of the memory cells read. For a new write operation, the controller determines if a reset on set write operation is to be performed. The controller also searches the lookup table to determine if an address for the target bits or codeword of the write operation are in the lookup table. If both conditions are satisfied, then the magnitude of the write pulse is increased for programming the memory cells.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: October 29, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Zhongyuan Lu, Robert John Gleixner
  • Publication number: 20240331781
    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.
    Type: Application
    Filed: June 14, 2024
    Publication date: October 3, 2024
    Inventors: Nevil N. Gajera, Karthik Sarpatwari, Zhongyuan Lu
  • Publication number: 20240312554
    Abstract: Methods, systems, and devices for efficient read disturb scanning are described. A memory system may limit a quantity of word lines scanned as part of a read disturb scan. For example, the memory system may select a threshold quantity of word lines of a block for the read disturb scan based on a characterization of the word lines, such as selecting one or more word lines having higher bit error rates than other word lines of the block. The memory system may perform the read disturb scan on the selected one or more word lines to determine respective failure bit counts of the selected word lines and exclude unselected word lines of the block from the read disturb scan. The memory system may determine whether to perform a refresh operation on the block based on whether a respective failure bit count satisfies a threshold failure bit count.
    Type: Application
    Filed: March 8, 2024
    Publication date: September 19, 2024
    Inventors: Chun Sum Yeung, Deping He, Zhongyuan Lu
  • Publication number: 20240296892
    Abstract: Bake temperatures for memory blocks can be determined as part of an operation to allocate memory blocks for us by a memory device. If a temperature of a particular memory block among the plurality of memory blocks meets or exceeds a threshold operational temperature corresponding to a memory device containing the plurality of memory blocks, the particular memory block can be allocated for receipt and/or storage of data.
    Type: Application
    Filed: May 9, 2024
    Publication date: September 5, 2024
    Inventors: Zhongyuan Lu, Niccolo' Righetti
  • Patent number: 12069570
    Abstract: A processing method and a processing device for saving energy of a base station are provided. The method includes: obtaining engineering parameter data and MR data of a base station; gridding the MR data to obtain grid MR data, and calculating a calculated value of longitude and latitude data of the base station according to the grid MR data; comparing the calculated value of the longitude and latitude data of the base station with longitude and latitude data of the base station in the engineering parameter data to select engineering parameter data, which is input into a load prediction model, of the base station; inputting the engineering parameter data of the base station selected into the load prediction model to train and predict the load prediction model; and issuing a corresponding power-saving turn-off strategy according to a prediction result of the load prediction model.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: August 20, 2024
    Assignee: CHINA TELECOM CORPORATION LIMITED
    Inventors: Jingjing Yuan, Zhongyuan Lu, Le Zhang, Ying Wang
  • Publication number: 20240256142
    Abstract: Methods, systems, and devices for managing partially programmed blocks are described. Based on writing data stored in a first block to a second block, a determination of whether to program the first block into a fully programmed state may be made based on whether the first block is storing the data in the partially programmed state. Based on determining whether to program the first block, the first block may be maintained in the fully programmed state until an erase operation is performed for the first block.
    Type: Application
    Filed: January 23, 2024
    Publication date: August 1, 2024
    Inventors: Chun Sum Yeung, Pitamber Shukla, Zhongyuan Lu, Niccolo' Righetti
  • Publication number: 20240242768
    Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including identifying an erased block of the memory array, causing a set of cells addressable by a target wordline of the erased block to be set to a target threshold voltage, determining an amount of threshold voltage shift with respect to the target threshold voltage after a delay, determining whether the amount of threshold voltage shift satisfies a threshold condition defined by a target data retention metric, and in response to determining that the amount of threshold voltage shift is sufficient, releasing the erased block for programming.
    Type: Application
    Filed: November 22, 2023
    Publication date: July 18, 2024
    Inventor: Zhongyuan Lu
  • Patent number: 12014784
    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Nevil N. Gajera, Karthik Sarpatwari, Zhongyuan Lu
  • Patent number: 12002516
    Abstract: Bake temperatures for memory blocks can be determined as part of an operation to allocate memory blocks for us by a memory device. If a temperature of a particular memory block among the plurality of memory blocks meets or exceeds a threshold operational temperature corresponding to a memory device containing the plurality of memory blocks, the particular memory block can be allocated for receipt and/or storage of data.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: June 4, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Zhongyuan Lu, Niccolo' Righetti
  • Patent number: 11978513
    Abstract: Apparatuses, methods, and systems for generating patterns for memory using threshold voltage difference are disclosed. An embodiment includes circuitry and a memory array including a plurality of memory cells. The circuitry can select a group of memory cells from the plurality of memory cells, program each memory cell of the group to a first data state, determine a first threshold voltage of each memory cell of the group, program each memory cell of the group to a second data state, perform a number of snapback events on each memory cell of the group, program each memory cell of the group to the first data state, determine a second threshold voltage of each memory cell of the group having the first data state, and generate a pattern for the memory array based, at least in part, on a difference between the first threshold voltage and the second threshold voltage.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Zhongyuan Lu, Robert J. Gleixner
  • Publication number: 20240096433
    Abstract: A memory device can include multiple memory cells and a processing device operatively coupled with the memory device to perform operations including grouping the memory cells into a groups based on a metric reflecting an electrical distance of a memory cell from a voltage source, and determining, for each group, a respective share of write operations, wherein the share of write operations is related to an aggregate value of the metric for memory cells of the group. The operations can also include distributing the write operations to each group according to the share of write operations determined for the group.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Zhongyuan Lu, Karthik Sarpatwari, Nevil N. Gajera
  • Publication number: 20240071491
    Abstract: Systems, methods, and apparatus to select an enhanced write pulse for a write operation in a memory device. In one approach, stronger reset pulses are triggered when there is an increased risk of memory cell threshold voltage degradation. Memory cells read by a relatively higher number of read operations are recorded by a controller of a memory device by updating a lookup table with addresses of the memory cells read. For a new write operation, the controller determines if a reset on set write operation is to be performed. The controller also searches the lookup table to determine if an address for the target bits or codeword of the write operation are in the lookup table. If both conditions are satisfied, then the magnitude of the write pulse is increased for programming the memory cells.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Zhongyuan Lu, Robert John Gleixner
  • Publication number: 20240071483
    Abstract: Disclosed are techniques for correcting drift accumulation in memory cells. In some aspects, the techniques described herein relate to a memory device including: a memory array, the memory array including a set of memory cells; and a memory controller configured to read data from the memory array, the memory controller configured to: sense a first distribution of the set of memory cells, detect a missing cell in the first distribution, increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution, detect that a second memory cell in a second distribution was read while sensing the first distribution, and mask the second memory cell and mark the second memory cell as belonging to the second distribution.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Christophe Vincent Antoine Laurent, Francesco Mastroianni, Andrea Martinelli, Efrem Bolandrina, Lucia Di Martino, Riccardo Muzzetto, Zhongyuan Lu, Karthik Sarpatwari, Nevil N. Gajera
  • Publication number: 20240040501
    Abstract: A processing method and a processing device for saving energy of a base station are provided. The method includes: obtaining engineering parameter data and MR data of a base station; gridding the MR data to obtain grid MR data, and calculating a calculated value of longitude and latitude data of the base station according to the grid MR data; comparing the calculated value of the longitude and latitude data of the base station with longitude and latitude data of the base station in the engineering parameter data to select engineering parameter data, which is input into a load prediction model, of the base station; inputting the engineering parameter data of the base station selected into the load prediction model to train and predict the load prediction model; and issuing a corresponding power-saving turn-off strategy according to a prediction result of the load prediction model.
    Type: Application
    Filed: July 27, 2021
    Publication date: February 1, 2024
    Inventors: Jingjing YUAN, Zhongyuan LU, Le ZHANG, Ying WANG
  • Patent number: 11875867
    Abstract: A memory device can include multiple memory cells and a processing device operatively coupled with the memory device to perform operations including grouping the memory cells into a groups based on a metric reflecting an electrical distance of a memory cell from a voltage source, and determining, for each group, a respective share of write operations, wherein the share of write operations is related to an aggregate value of the metric for memory cells of the group. The operations can also include distributing the write operations to each group according to the share of write operations determined for the group.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: January 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Zhongyuan Lu, Karthik Sarpatwari, Nevil N. Gajera
  • Publication number: 20230395156
    Abstract: Bake temperatures for memory blocks can be determined as part of an operation to allocate memory blocks for us by a memory device. If a temperature of a particular memory block among the plurality of memory blocks meets or exceeds a threshold operational temperature corresponding to a memory device containing the plurality of memory blocks, the particular memory block can be allocated for receipt and/or storage of data.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Zhongyuan Lu, Niccolo' Righetti
  • Patent number: 11823761
    Abstract: Systems, methods, and apparatus to evaluate read margin when reading memory cells in a memory device. In one approach, a controller of a memory device applies an initial read voltage of an initial polarity to memory cells. Errors from the read are used to determine whether read retry is needed. If so, a pre-read voltage of an opposite polarity is applied, and errors determined. Based on the errors from applying the pre-read voltage, a polarity is selected for the read retry voltage. The read retry voltage of the selected polarity is then applied to the memory cells.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: November 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Zhongyuan Lu, Robert John Gleixner
  • Patent number: 11823745
    Abstract: The present disclosure includes apparatuses, methods, and systems for predicting and compensating for degradation of memory cells. An embodiment includes a memory having a group of memory cells, and circuitry configured to, upon a quantity of sense operations performed on the group of memory cells meeting or exceeding a threshold quantity, perform a sense operation on the group of memory cells using a positive sensing voltage and perform a sense operation on the group of memory cells using a negative sensing voltage, and perform an operation to program the memory cells of the group determined to be in a reset data state by both of the sense operations to the reset data state.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: November 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Zhongyuan Lu, Robert J. Gleixner
  • Patent number: 11762779
    Abstract: Various embodiments enable read buffering in connection with data block transfer on a memory device. For some embodiments, read buffering from a set of cache blocks is enabled during a period of wait time after data is copied (e.g., data is transferred, such as part of a compaction operation) from the set of cache blocks to a set of non-cache blocks. In various embodiments, after the wait time, data stored on the set of cache blocks is erased (e.g., the set of cache blocks is released) and read buffering from the set of cache blocks is disabled.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Zhongyuan Lu, Niccolo' Righetti
  • Publication number: 20230268006
    Abstract: Apparatuses, methods, and systems for generating patterns for memory using threshold voltage difference are disclosed. An embodiment includes circuitry and a memory array including a plurality of memory cells. The circuitry can select a group of memory cells from the plurality of memory cells, program each memory cell of the group to a first data state, determine a first threshold voltage of each memory cell of the group, program each memory cell of the group to a second data state, perform a number of snapback events on each memory cell of the group, program each memory cell of the group to the first data state, determine a second threshold voltage of each memory cell of the group having the first data state, and generate a pattern for the memory array based, at least in part, on a difference between the first threshold voltage and the second threshold voltage.
    Type: Application
    Filed: February 24, 2022
    Publication date: August 24, 2023
    Inventors: Zhongyuan Lu, Robert J. Gleixner