Abstract: A capacitive sensing device comprises first electrodes in which a plurality of first sensing elements are arranged in rows and columns, and second electrodes in which a plurality of second sensing elements are arranged in rows and columns. Each of the first sensing elements has an iron cross shape, and each of the second sensing elements has a double-cross shape in which a first cross and a second cross overlap each at a shared center point and the second cross is rotated with respect to the first cross. Capacitances are formed between the first sensing elements and the second sensing elements.

Abstract: A display driver integrated circuit using a ping-pong type sample and hold circuit is provided. The display driver integrated circuit includes a data counter, a comparison unit, a gray voltage generation unit, and a sample and hold circuit. The data counter outputs first through n-th gamma data in response to a clock signal. The comparison unit compares input image data with each of the first through n-th gamma data so as to output a comparison signal. The gray voltage generation unit generates first through n-th gray voltages in response to the first through n-th gamma data. The sample and hold circuit includes a first sub sample and hold circuit and a second sub sample and hold circuit and outputs one of the first through n-th gray voltages in response to the comparison signal.

Abstract: A capacitive sensing device comprises first electrodes in which a plurality of first sensing elements are arranged in rows and columns, and second electrodes in which a plurality of second sensing elements are arranged in rows and columns. Each of the first sensing elements has an iron cross shape, and each of the second sensing elements has a double-cross shape in which a first cross and a second cross overlap each at a shared center point and the second cross is rotated with respect to the first cross. Capacitances are formed between the first sensing elements and the second sensing elements.

Abstract: A display driver integrated circuit using a ping-pong type sample and hold circuit is provided. The display driver integrated circuit includes a data counter, a comparison unit, a gray voltage generation unit, and a sample and hold circuit. The data counter outputs first through n-th gamma data in response to a clock signal. The comparison unit compares input image data with each of the first through n-th gamma data so as to output a comparison signal. The gray voltage generation unit generates first through n-th gray voltages in response to the first through n-th gamma data. The sample and hold circuit includes a first sub sample and hold circuit and a second sub sample and hold circuit and outputs one of the first through n-th gray voltages in response to the comparison signal.

Abstract: A cyclic digital to analog converter (CDAC) in a pipeline structure includes a first CDAC block and a second CDAC block. The first CDAC block receives a first digital signal and converts the first digital signal to a first analog value. The first CDAC block includes a charging capacitor for charging according to the first digital signal and a first storing capacitor for storing the first analog value. The second CDAC block receives a second digital signal and converts the second digital signal to a second analog value. The second CDAC block includes the charging capacitor for charging according to the second digital signal and a second storing capacitor for storing the second analog value. The first CDAC block and the second CDAC block share the charging capacitor.

Abstract: A cyclic digital to analog converter (CDAC) in a pipeline structure includes a first CDAC block and a second CDAC block. The first CDAC block receives a first digital signal and converts the first digital signal to a first analog value. The first CDAC block includes a charging capacitor for charging according to the first digital signal and a first storing capacitor for storing the first analog value. The second CDAC block receives a second digital signal and converts the second digital signal to a second analog value. The second CDAC block includes the charging capacitor for charging according to the second digital signal and a second storing capacitor for storing the second analog value. The first CDAC block and the second CDAC block share the charging capacitor.

Abstract: A cyclic digital to analog converter (CDAC) includes: first and second capacitors C1 and C2; an arrangement of switches selectively controllable to connect C1 and C2 in one of at least two charging-and-sharing configurations, the first configuration having the first capacitor C1 as a charging capacitor CCH and the second capacitor C2 as a sharing capacitor CSH, namely CCH=C1 and CSH=C2, and the second configuration having CCH=C2 and CSH=C1; and a controller to toggle the arrangement of switches between the first and second configurations based upon adjacent bits of a given input word.