Abstract: An apparatus for enqueuing kernels on a device-side is introduced to incorporate with at least a MXU (Memory Access Unit) and a CSP (Command Stream Processor): The CSP, after receiving a first command from the MXU, executes commands of a ring buffer, thereby enabling an EU (Execution Unit) to direct the MXU to allocate space of the ring buffer for a first hardware thread and subsequently write second commands of the first hardware thread into the allocated space of the ring buffer according to an instruction of a kernel.

Abstract: Aspects of the disclosure provide a circuit that includes a processing circuit, a memory directly coupled to the processing circuit via a dedicated data bus and a control circuit. The processing circuit includes a dot product engine. The dot product engine is configured to perform, in response to an instruction, an operation that includes dot product calculations on a weight input and a pixel sample input, and to store a result of the operation into the memory. The control circuit is configured to control the dot product engine to perform arithmetic operations that include the dot product calculations, and control the dot product engine to perform an accumulation of outputs of the dot product calculations and data received from the memory via the dedicated data bus to generate the result of the operation.

Abstract: A graphic data compression device includes a processing unit for processing graphic data and a mixed-type compression unit for compressing the data processed by the processing unit. The mixed-type compression unit includes a lossless compression module and a nearly-lossless compression module. The lossless compression module performs a compression on processed data by a lossless compression algorithm. The nearly-lossless compression module includes an adjustment module and a compression module. The adjustment module performs an adjustment on the processed data to reduce a size of the processed data. The compression module performs, by the lossless compression algorithm, a compression on the data adjusted by the adjustment module. A graphic data compression method of the graphic data compression device is also provided. The graphic data compression device and method of the present invention reduce bandwidth load and memory occupancy, thereby effectively improving the usage of memory capacity.

Abstract: An image compression method based on JPEG-LS is presented. In the method, the M×N pixels in the source image are divided into k groups. M, N, and k are all integers larger than one. Each group corresponds to a plurality of pixels among the M×N pixels. The decorrelation procedure and the context modeling procedure are performed for each of the plurality of pixels in the ith group of the k groups. The compensation look-up table is not refreshed until all pixels in the ith group are performed with the decorrelation procedure and the context modeling procedure.

Abstract: A graphics processing system and power gating method thereof, the graphics processing system comprising: a graphics processing unit (GPU), a bus interface and a power management unit (PMU), the GPU comprising a control circuit and a plurality of partitions; the method includes: when the bus interface receives an external graphics command, utilizing the PMU to turn on a power supply of the control circuit; subsequently utilizing the control circuit to turn on power supplies of one or more partitions of the plurality of partitions corresponding to the external graphics command; when then control circuit detects any one of the plurality of partitions is in an idle state, utilizing the control circuit to turn off the power supply of the partition in the idle state; when the bus interface detects the plurality of partitions are in a full idle state, utilizing the bus interface to turn off the power supply of the control circuit via the PMU; and when the PMU turns off the power supply of the control circuit, the co

Abstract: A dynamic voltage frequency scaling (DVFS) system is provided. The DVFS system includes: a computation unit, a power management unit (PMU), a hardware activity monitor (HAM), and a hardware voltage monitor (HVM). The HAM monitors a working status and temperature information of the computation unit, and determines whether to update an operating voltage and frequency of the computation unit according to the working status, the temperature information, and a previous determination result. When the HAM determines to update the operating voltage and frequency, the HAM generates a first control signal to the PMU to calibrate the operating voltage and frequency. The HVM detects timing information of the computation unit and determine whether to fine-tune the operating voltage according to the detected timing information. When the HVM determines to fine-tune the operating voltage, the hardware monitor generates a second control signal to the PMU to fine-tune the operating voltage.

Abstract: A graphics processing unit and associated graphics processing method are provided. The graphics processing unit includes: an execution unit, for performing shader execution and texture loading; a fixed-function unit, for executing a graphics rendering pipeline; a memory-access unit; a texture unit, for reading texture data from a memory via the memory-access unit according to the data requirement of the execution unit or the fixed-function unit; and a command stream parser, for receiving a draw command from a display driver, and transmitting the draw command to the execution unit or the fixed-function unit to perform graphics processing according to the type of draw command. When the command stream parser determines that the draw command is a specific draw command, the command stream parser transmits the draw command only to the fixed-function unit to perform graphics processing, and turns off power to the execution unit.

Abstract: A computing resource controller controlling how multiple engines share a shared resource. The controller has an arbiter, a monitoring module, an arbiter strategy control center, and an arbiter parameter updating module. The arbiter allocates access rights to the shared resource to the engines. The monitor module monitors the demands for the shared resource requested by the engines. Based on monitored results obtained from the monitoring module, the arbiter strategy control center determines an arbiter strategy suitable to the arbiter and, accordingly, the arbiter parameter updating module sets parameters of the arbiter, and the arbiter uses newly-set parameters to allocate the access rights to the shared resource to the engines.

Abstract: A device for image processing includes a first queue, a second queue, a cache, and a processor. The first queue is capable of receiving a first image tile. The processor is electrically connected to the first queue, the second queue, and the cache, respectively. The processor is capable of obtaining the first image tile from the first queue and obtaining mask information of the background mask corresponding to the first tile from the cache. The processor determines the relationship between the first image tile and the background mask based on the first image tile and the mask information so as to selectively transfer the first image tile to the second queue.

Abstract: A method for combining instructions, performed by a compiler, containing at least the following steps. First instructions are obtained, where each performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST (Load/Store) operation, a SMP (sampling) operation and a complicated mathematics operation. The first instructions are combined as one combined instruction according to data dependencies between the first instructions. The combined instruction is sent to a SP (Stream Processor).

Abstract: A method for a programmable primitive setup in a 3D graphics pipeline is introduced to contain at least the following steps. Information about first and third primitives is obtained from a buffer. The information about all or a portion of the first primitives is packed and sent to an SS (Setup Shader) thread. Information about a second primitive to be clipped is packed and sent to a GBS (Guard-Band-clipping Shader) thread. The information about all or a portion of the third primitives is packed and sent to an AS (Attribute Shader) thread.

Abstract: An on-chip sensor hub fabricated on a chip with a main processor of a mobile device, and the mobile device, and a method for multi-sensor management on the mobile device. An on-chip sensor hub includes a co-processor and uses an inter-process communication interface. The co-processor and main processor of the mobile device are fabricated on the same chip and communicate with each other via the inter-process communication interface. The co-processor controls a plurality of sensors in the mobile device in accordance with requests issued from the main processor. The co-processor further collects and manages sensor data from the sensors to be processed by the main processor.

Abstract: A graphics processing system and a power gating method thereof is provided. The graphics processing system includes a bus interface, a graphics processing unit, and a power management unit. The graphics processing unit includes a plurality of partitions and a control circuit. When the bus interface has received an external graphics processing command, the bus interface informs the power management unit to turn on power to the control circuit. The control circuit turns on power to one or more of the partitions corresponding to the external graphics processing command after analyzing the external graphics processing command. The control circuit turns off power to the partitions in the idle state when detecting that one of the partitions is in the idle state. The bus interface turns off the power to the control circuit via the power management circuit when detecting that the partitions are in a full idle state.

Abstract: An image compression method based on JPEG-LS is presented. In the method, the M×N pixels in the source image are divided into k groups. M, N, and k are all integers larger than one. Each group corresponds to a plurality of pixels among the M×N pixels. The decorrelation procedure and the context modeling procedure are performed for each of the plurality of pixels in the ith group of the k groups. The compensation look-up table is not refreshed until all pixels in the ith group are performed with the decorrelation procedure and the context modeling procedure.

Abstract: A device for image processing includes a first queue, a second queue, a cache, and a processor. The first queue is capable of receiving a first image tile. The processor is electrically connected to the first queue, the second queue, and the cache, respectively. The processor is capable of obtaining the first image tile from the first queue and obtaining mask information of the background mask corresponding to the first tile from the cache. The processor determines the relationship between the first image tile and the background mask based on the first image tile and the mask information so as to selectively transfer the first image tile to the second queue.

Abstract: A computing resource controller controlling how multiple engines share a shared resource. The controller has an arbiter, a monitoring module, an arbiter strategy control center, and an arbiter parameter updating module. The arbiter allocates access rights to the shared resource to the engines. The monitor module monitors the demands for the shared resource requested by the engines. Based on monitored results obtained from the monitoring module, the arbiter strategy control center determines an arbiter strategy suitable to the arbiter and, accordingly, the arbiter parameter updating module sets parameters of the arbiter, and the arbiter uses newly-set parameters to allocate the access rights to the shared resource to the engines.

Abstract: An apparatus for enqueuing kernels on a device-side is introduced to incorporate with at least a MXU (Memory Access Unit) and a CSP (Command Stream Processor): The CSP, after receiving a first command from the MXU, executes commands of a ring buffer, thereby enabling an EU (Execution Unit) to direct the MXU to allocate space of the ring buffer for a first hardware thread and subsequently write second commands of the first hardware thread into the allocated space of the ring buffer according to an instruction of a kernel.

Abstract: A graphic data compression device includes a processing unit for processing graphic data and a mixed-type compression unit for compressing the data processed by the processing unit. The mixed-type compression unit includes a lossless compression module and a nearly-lossless compression module. The lossless compression module performs a compression on processed data by a lossless compression algorithm. The nearly-lossless compression module includes an adjustment module and a compression module. The adjustment module performs an adjustment on the processed data to reduce a size of the processed data. The compression module performs, by the lossless compression algorithm, a compression on the data adjusted by the adjustment module. A graphic data compression method of the graphic data compression device is also provided. The graphic data compression device and method of the present invention reduce bandwidth load and memory occupancy, thereby effectively improving the usage of memory capacity.

Abstract: A method for combining instructions, performed by a compiler, containing at least the following steps. First instructions are obtained, where each performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST (Load/Store) operation, a SMP (sampling) operation and a complicated mathematics operation. The first instructions are combined as one combined instruction according to data dependencies between the first instructions. The combined instruction is sent to a SP (Stream Processor).

Abstract: A method for a programmable primitive setup in a 3D graphics pipeline is introduced to contain at least the following steps. Information about first and third primitives is obtained from a buffer. The information about all or a portion of the first primitives is packed and sent to an SS (Setup Shader) thread. Information about a second primitive to be clipped is packed and sent to a GBS (Guard-Band-clipping Shader) thread. The information about all or a portion of the third primitives is packed and sent to an AS (Attribute Shader) thread.