Abstract: Disclosed are antigen binding polypeptides and antigen binding polypeptide complexes (e.g., antibodies and antigen binding fragments thereof) having certain structural and/or functional features. Also disclosed are polynucleotides and vectors encoding such polypeptides and polypeptide complexes; host cells, pharmaceutical compositions and kits containing such polypeptides and polypeptide complexes; and methods of using such polypeptides and polypeptide complexes.

Abstract: The present disclosure relates to a surface-enhanced Raman spectroscopy complex probe capable of effectively detecting a catecholamine compound even at extremely low concentrations. The complex probe includes a nanolaminate including a nanogap and metal nanoparticles. In this case, the nanolaminate and the metal nanoparticles are modified to a compound that may be bound to each functional group included in catecholamine, and thus, catecholamine included in an analyte is doubly recognized by the complex probe. In addition, since a hotspot emitting a strong SERS signal is formed by a nanogap included in a nanolaminate, it is possible to effectively detect a catecholamine compound even at extremely low concentrations.

Abstract: A membrane circuit board includes a first film substrate, a second film substrate, an insulating spacer substrate and a waterproof structure. The first circuit layer is installed on the first film substrate. A second circuit layer is installed on the second film substrate. The insulating spacer substrate arranged between the first film substrate and the second film substrate. The first circuit layer is arranged between the first film substrate and the insulating spacer substrate. The second circuit layer is arranged between the second film substrate and the insulating spacer substrate. The waterproof structure includes a first welding layer and a second welding layer. The first welding layer is arranged between the first film substrate and the insulating spacer substrate. The second welding layer is arranged between the second film substrate and the insulating spacer substrate.

Abstract: A membrane circuit board includes a first film substrate, a second film substrate, an insulating spacer substrate and a waterproof structure. The first circuit layer is installed on the first film substrate. A second circuit layer is installed on the second film substrate. The insulating spacer substrate arranged between the first film substrate and the second film substrate. The first circuit layer is arranged between the first film substrate and the insulating spacer substrate. The second circuit layer is arranged between the second film substrate and the insulating spacer substrate. The waterproof structure includes a first welding layer and a second welding layer. The first welding layer is arranged between the first film substrate and the insulating spacer substrate. The second welding layer is arranged between the second film substrate and the insulating spacer substrate.

Abstract: An underwater propulsion apparatus includes a motor and a control system for controlling the motor. The control system includes a remote controller and a motor driving device, wirelessly communicating with the remote controller. The motor driving device includes a communication repeater module and a motor driving module. The communication repeater module is configured for detecting interruptions or non-receipt of a wireless signal transmitted by the remote controller. Wireless signals to the motor driving module are transmitted by the remote controller to the communication repeater module. The motor driving module is configured for receiving the wireless signal, and outputs a driving signal for driving the motor according to the wireless signal, the motor driving module shutting down when no signal is received.

Abstract: An underwater propulsion apparatus includes a motor and a control system for controlling the motor. The control system includes a remote controller and a motor driving device, wirelessly communicating with the remote controller. The motor driving device includes a communication repeater module and a motor driving module. The communication repeater module is configured for detecting interruptions or non-receipt of a wireless signal transmitted by the remote controller. Wireless signals to the motor driving module are transmitted by the remote controller to the communication repeater module. The motor driving module is configured for receiving the wireless signal, and outputs a driving signal for driving the motor according to the wireless signal, the motor driving module shutting down when no signal is received.

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract: A method of alarm management in a communications system having a number of Femto base stations (110), the method comprising the steps of: detecting disruption of a communication link between a Femto base station and a management system (120) via which alarms are communicated; blocking the sending of alarms by the Femto base station; generating a report representative of the accumulation of alarms; detecting re-establishment of the communication link; sending the report to the management system; and reporting alarms to the management system on the basis of the report.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: The invention includes methods of forming semiconductor interconnect structures. A substrate is provided having metal bumps associated with contact pads. A plate having a plurality of cavities containing solder is provided. The metal bumps are inserted into the cavities. The invention includes methods of forming surface-mounting structures. A wafer having a plurality of dies is provided. Each die has contact pads with associated projecting metal bumps. A plate is provided having a pattern of solder-filled cavities corresponding to a layout of the contact pads. The metal bumps are inserted into the cavities and the solder is reflowed to form metal-cored solder bumps. The invention includes constructions such as integrated circuitry chips, wafers and chip package assemblies having a plurality of interconnect structures. The interconnect structures comprise a metal core within an outer solder bump, and are electrically and physically associated with contact pads.

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.