Abstract: A linker peptide for constructing a fusion protein. The linker peptide comprises a flexible peptide and a rigid peptide. The flexible peptide consists of one or more flexible units. The rigid peptide consists of one or more rigid units. The flexible unit comprises two or more amino acid residues selected from Gly, Ser, Ala, and Thr. The rigid unit comprises a human chorionic gonadotropin ?-subunit carboxy-terminal peptide (CTP) bearing a plurality of glycosylation sites. The linker peptide can more effectively eliminate mutual steric hindrance of two fusion molecules, decreasing a reduction/loss of polymerization or activity resulting from improper folding of an active protein or a conformational change. On the other hand, the negatively charged, highly sialylated CTP can resist renal clearance, further prolonging a half-life of a fused molecule and enhancing bioavailability of a fused protein.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device includes the following operations. A dielectric stack is formed to have interleaved sacrificial layers and dielectric layers. A stair is formed in the dielectric stack. The stair includes one or more sacrificial layers of the sacrificial layers and one or more dielectric layers of the dielectric layers. The stair exposes one of the sacrificial layers on a top surface and the one or more sacrificial layers on a side surface. An insulating portion is formed to cover the side surface of the stair to cover the one or more sacrificial layers. A sacrificial portion is formed to cover the top surface of the stair. The sacrificial portion is in contact with the one of sacrificial layers. The one or more sacrificial layers and the sacrificial portion are replaced with one or more conductor layers.

Abstract: A heart valve prosthesis delivery device can be modified in situ to facilitate retrieval of the device from a patient after delivery of a heart valve prosthesis. The device can include a nose cone that permits enclosures of the device to be drawn together in an aligned configuration, reducing the likelihood that the device will get caught on the prosthesis or vasculature as the device is retrieved from the patient.

Abstract: The present application discloses a vehicle-mounted heterogeneous network collaborative task unloading method, which comprises the following steps: calculating a communication delay when a vehicle requests a cache from a smart lamp post for a vehicle terminal; taking the maximum communication delay in all the caches as the communication delay between the vehicle and the smart lamp post network, and determining whether the communication delay is less than the time when the vehicle sends a request to a cloud center, if so, unloading a task to the smart lamp post network, otherwise, unloading a task to the cloud center; taking profit of a single smart lamp post itself as an index for the smart lamp post terminal, dividing the smart lamp post network into a plurality of coalitions, taking the profit maximization of the coalition as an optimization objective, optimizing a smart lamp post combination in the coalition.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. The methods can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC); performing a thermal simulation for each respective template of the IC based on a sequence of power patterns of tiles of the respective template; and training a neural network with a plurality of training data collected via thermal simulations performed for the templates of the IC. These systems and methods can use a machine learning predictor, that has been trained to determine a transient temperature rise across an entire IC, and then append the determined transient temperature rise to a system level thermal profile of the IC.

Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a semiconductor layer, a memory stack over the semiconductor layer, first channel structures each extending vertically through the memory stack in an edge region, and an isolation structure. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. At least one of conductive layers toward the semiconductor layer is a source select gate line (SSG). The isolation structure extends vertically through the SSG and into the semiconductor layer. The memory stack includes a core array region, a staircase region, and the edge region being laterally between the core array region and the staircase region. At least one of the first channel structures extends through the isolation structure and is separated from the SSG through the isolation structure.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.

Abstract: A method of fabricating a three-dimensional memory includes forming a laminated structure including stacked dummy gate layers and interlayer insulation layers on one side of a substrate. The respective adjacent dummy gate layers and interlayer insulation layers form staircase stairs. At least a part of the interlayer insulation layer of each of the staircase stairs is exposed. The method also includes forming a buffer layer covering the staircase stairs. The method further includes removing a part of the buffer layer covering the sidewalls of the staircase stairs to form spacing grooves. The method further includes forming a dielectric layer that fills the spacing grooves and covers the staircase stairs. The method further includes forming a contact hole penetrating through the dielectric layer and the buffer layer and extending to the dummy gate layer farthest from the substrate.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a memory stack having a plurality of stairs. Each stair may include interleaved one or more conductor layers and one or more dielectric layers. Each of the stairs includes one of the conductor layers on a top surface of the stair, the one of the conductor layers having (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion exposed by the memory stack and in contact with the bottom portion. A lateral dimension of the top portion may be less than a lateral dimension of the bottom portion. An end of the top portion that may be facing away from the memory stack laterally exceeds the bottom portion by a distance.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a memory stack having a plurality of stairs. Each stair may include interleaved one or more conductor layers and one or more dielectric layers. Each of the stairs includes one of the conductor layers on a top surface of the stair, the one of the conductor layers having (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion exposed by the memory stack and in contact with the bottom portion. A lateral dimension of the top portion may be less than a lateral dimension of the bottom portion. An end of the top portion that may be facing away from the memory stack laterally exceeds the bottom portion by a distance.

Abstract: A vacuum clear and an electric motor module (100) therefor are provided. The electric motor module (100) includes an outer casing (1) provided with an air inlet (10) at a front side thereof and an air outlet (11) at a rear side thereof; an electric motor assembly (2) arranged in the outer casing (1), and cooperating with the outer casing (1) to define an air passage in communication with the air inlet (10) and the air outlet (11); and a silencer (3) arranged at the air inlet (10), defining at least one resonant cavity therein, and the at least one resonant cavity having a side wall provided with a throat in communication with the resonant cavity.

Abstract: Aspects of the disclosure provide semiconductor devices. For example, a semiconductor device includes a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate. Then, the semiconductor device includes a memory stack that includes a first stack of alternating gate layers and insulating layers and a second stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate. Further, the semiconductor device includes a joint insulating layer in the second region and a third stack of alternating gate layers and insulating layers in the first region between the first stack of alternating gate layers and insulating layers and the second stack of alternating gate layers and insulating layers.

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory. In an example, the method includes forming a stack structure having interleaved a plurality of stack first layers and a plurality of stack second layers, forming a stair in the stack structure, the stair having one of the stack first layers on a top surface, and forming a layer of sacrificial material having a first portion over a side surface of the stair and a second portion over the top surface of the stair. The method also includes partially removing the first portion of the layer of sacrificial material using an anisotropic etching process and removing a remaining portion of the first portion of the layer of sacrificial material using an isotropic etching process.

Abstract: Aspects of the disclosure provide methods for fabricating semiconductor devices. In some examples, a method for fabricating a semiconductor device includes forming a stack of layers having a first region and a second region. The stack of layers includes at least a first layer. The method then forms a hard mask layer on the stack of layers in the first region. Then, the method includes patterning the stack of layers in the second region of the semiconductor device. The patterning of the stack of layers in the second region removes a portion of the stack of layers in the second region, and exposes a side of the stack of layers. The method further includes covering at least the side of the stack of layers with a second layer that has a lower remove rate than the first layer, and then the method includes removing the hard mask layer.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.

Abstract: Disclosed are a multi-stage gravity-type sludge drying apparatus and a sludge drying method using the same. The drying apparatus includes: a dryer, a preheater, a steam generator, a filter, a steam or water separation buffer tank, a steam compressor, a cooling water pump, a sealed discharge device, pipes and valves. The dryer includes several indirect dryer modules. The transportation of sludge in the dryer is achieved by gravity. The inner cavity of respective indirect dryers is filled with high-temperature steam to dry the sludge by indirect heating. The condensate water in the cavity is recycled and fed into the preheater to perform preheating and impurity removal on the wet sludge. The secondary steam generated in the dryer is filtered, compressed and overheated to become a new heat source for indirect heating in the cavity and convection drying at a bottom of the dryer.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device includes the following operations. A dielectric stack is formed to have interleaved sacrificial layers and dielectric layers. A stair is formed in the dielectric stack. The stair includes one or more sacrificial layers of the sacrificial layers and one or more dielectric layers of the dielectric layers. The stair exposes one of the sacrificial layers on a top surface and the one or more sacrificial layers on a side surface. An insulating portion is formed to cover the side surface of the stair to cover the one or more sacrificial layers. A sacrificial portion is formed to cover the top surface of the stair. The sacrificial portion is in contact with the one of sacrificial layers. The one or more sacrificial layers and the sacrificial portion are replaced with one or more conductor layers.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a memory stack having a plurality of stairs. Each stair may include interleaved one or more conductor layers and one or more dielectric layers. Each of the stairs includes one of the conductor layers on a top surface of the stair, the one of the conductor layers having (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion exposed by the memory stack and in contact with the bottom portion. A lateral dimension of the top portion may be less than a lateral dimension of the bottom portion. An end of the top portion that may be facing away from the memory stack laterally exceeds the bottom portion by a distance.

Abstract: Disclosed are a multi-stage gravity-type sludge drying apparatus and a sludge drying method using the same. The drying apparatus includes: a dryer, a preheater, a steam generator, a filter, a steam or water separation buffer tank, a steam compressor, a cooling water pump, a sealed discharge device, pipes and valves. The dryer includes several indirect dryer modules. The transportation of sludge in the dryer is achieved by gravity. The inner cavity of respective indirect dryers is filled with high-temperature steam to dry the sludge by indirect heating. The condensate water in the cavity is recycled and fed into the preheater to perform preheating and impurity removal on the wet sludge. The secondary steam generated in the dryer is filtered, compressed and overheated to become a new heat source for indirect heating in the cavity and convection drying at a bottom of the dryer.