Abstract: An autonomous mobile robot control method and apparatus, a device and a readable storage medium. An autonomous mobile robot determines a sound source direction according to a voice signal from a user, and determines moving objects around the autonomous mobile robot itself. The autonomous mobile robot determines, from the moving objects, a target object located in the sound source direction, determines a working area according to the target object, and moves to the working area, and executes a task.

Abstract: A blood characteristic measurer includes multiple light sources, a light sensor and a processor. The multiple light sources emit multiple beams of light of different dominant lightening wavelength. The light sensor receives multiple reflected light beams due to the reflection of incident light from a skin surface. The processor is electrically coupled to the light sensor and produces the blood characteristic according to reconstructed spectra generated by the multiple reflected light beams and absorption coefficient spectra generated by the skin surface.

Abstract: The present application provides a processing method of a metal composite structure including a first metal layer and a second metal layer stacked on the first metal layer. The processing method includes the steps of defining a first through hole in the first metal layer, and drilling in the first through hole toward the second metal layer to form a traction hole in the second metal layer. Then, hot melt drilling is performed on a surface of the second metal layer away from the first metal layer toward the first through hole, thereby causing the second metal layer to crack under a traction force of the traction hole to form a second through hole, and a portion of the second metal layer to be melted and squeezed to form a bushing which adheres to at least a portion of a sidewall of the first through hole.

Abstract: Disclosed are compounds of Formula (I): or stereoisomers, tautomers, or salts thereof, wherein: R is and Ring A, L, R1, R2, R3, m, and n are defined herein. Also disclosed are methods of using such compounds to decrease the level Cyclin E1; and pharmaceutical compositions comprising such compounds. These compounds are useful in the treatment of proliferative disorders, such as cancer.

Abstract: A session shared data system accesses a first communication between a user and a support agent on a first communication channel and stores communication data associated with the first communication in a session shared data object. The session shared data system accesses a subsequent communication between the user and a second agent on a second communication channel, receives a query associated with the subsequent communication and transmits the response to a device of the second agent.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.

Abstract: The present disclosure relates to methods of treating a patient that has a low coronary ostia height. The methods can involve advancing a heart valve prosthesis to a native valve structure having an ostium and positioning the prosthesis to align a gap between major peaks of the prosthesis with the ostium to avoid obstruction of the ostium. The presently disclosed methods and prostheses can be effective at treating patients with a coronary ostia height of as low as 10 mm, 8 mm, 6 mm, or less.

Abstract: A display panel, including: a substrate base plate; touch electrodes; touch lead wires on the substrate base plate, one end of the touch lead wire is coupled with the touch electrode, the other end thereof is in a peripheral area, the touch lead wires in the display panel are divided into touch lead wire sets, each touch lead wire set includes touch lead wires; data lead wires on the substrate base plate in the peripheral area, the data lead wires are divided into data lead wire sets, each data lead wire set includes data lead wires, the touch lead wire sets and the data lead wire sets are distributed in a staggered manner; at least one shielding line on the substrate base plate in the peripheral area, an orthographic projection of the shielding line is between orthographic projections of the touch lead wire and the data lead wire.

Abstract: A method for forming a memory device is disclosed. A stack structure including interleaved first layers and second layers is formed. A staircase structure including stairs at an edge of the stack structure is formed. Each stair has one of the first layers on a top surface of the stair. A third layer including vertical portions covering side surface of the stairs and lateral portions covering the top surface of the stairs is formed. The third layer includes a first sublayer in contact with the stair and a second sublayer in contact with the first sublayer and on the first sublayer. A mask covering the vertical portions and the lateral portions of the third layer is formed. A portion of the mask covering the vertical portions of the third layer is removed to expose the vertical portions of the third layer. Vertical portions of the first sublayer are removed using a first etching process. Vertical portions of the second sublayer are removed using a second etching process.

Abstract: Systems, methods, and circuitries are provided for supporting blind retransmission. In one example, a method includes determining one or more communication parameters for use in communicating with a user equipment (UE) based on whether hybrid automatic repeat request (HARQ) feedback is enabled for the UE; and using at least one of the one or more communication parameters when HARQ feedback is determined to be enabled.

Abstract: Provided are a secondary cured UV pressure-sensitive adhesive, and preparation methods for same and an explosion-proof film. The secondary cured UV pressure-sensitive adhesive is composed of the following materials, in percentages by mass: 31-35% of a hydroxyl-containing polyacrylate prepolymer, 6-9% of pentaerythritol triacrylate, 3-5% of 2-hydroxyl-3-phenoxy propane acrylate, 2-3% of an isocyanate curing agent, 2-3% of photo initiator 184, and 50% of ethyl acetate. The secondary cured UV pressure-sensitive adhesive is prepared by carrying out a thermal curing cross-linking reaction of a hydroxyl-containing polyacrylate prepolymer, pentaerythritol triacrylate and 2-hydroxyl-3-phenoxy propane acrylate by using an isocyanate curing agent, and initiating a free radical polymerization of pentaerythritol triacrylate and 2-hydroxyl-3-phenoxy propane acrylate by using photo initiator 184.

Abstract: Aspects of the disclosure provide methods for fabricating semiconductor devices. In some examples, a method for fabricating a semiconductor device includes forming a stack of layers having a first region and a second region. The stack of layers includes at least a first layer. The method then forms a hard mask layer on the stack of layers in the first region. Then, the method includes patterning the stack of layers in the second region of the semiconductor device. The patterning of the stack of layers in the second region removes a portion of the stack of layers in the second region, and exposes a side of the stack of layers. The method further includes covering at least the side of the stack of layers with a second layer that has a lower remove rate than the first layer, and then the method includes removing the hard mask layer.

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory. In an example, the method includes forming a stack structure having interleaved a plurality of stack first layers and a plurality of stack second layers, forming a stair in the stack structure, the stair having one of the stack first layers on a top surface, and forming a layer of sacrificial material having a first portion over a side surface of the stair and a second portion over the top surface of the stair. The method also includes partially removing the first portion of the layer of sacrificial material using an anisotropic etching process and removing a remaining portion of the first portion of the layer of sacrificial material using an isotropic etching process.

Abstract: Aspects of the disclosure provide semiconductor devices. For example, a semiconductor device includes a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate. Then, the semiconductor device includes a memory stack that includes a first stack of alternating gate layers and insulating layers and a second stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate. Further, the semiconductor device includes a joint insulating layer in the second region and a third stack of alternating gate layers and insulating layers in the first region between the first stack of alternating gate layers and insulating layers and the second stack of alternating gate layers and insulating layers.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a stack structure including alternating conductive layers and dielectric layers and having at least two core regions and a staircase region between the two core regions, and bridge structures connecting the two core regions and extending through the staircase region in a first direction. A first bridge structure of the bridge structures includes at least two current paths between the two core regions.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device includes the following operations. A dielectric stack is formed to have interleaved sacrificial layers and dielectric layers. A stair is formed in the dielectric stack. The stair includes one or more sacrificial layers of the sacrificial layers and one or more dielectric layers of the dielectric layers. The stair exposes one of the sacrificial layers on a top surface and the one or more sacrificial layers on a side surface. An insulating portion is formed to cover the side surface of the stair to cover the one or more sacrificial layers. A sacrificial portion is formed to cover the top surface of the stair. The sacrificial portion is in contact with the one of sacrificial layers. The one or more sacrificial layers and the sacrificial portion are replaced with one or more conductor layers.

Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a semiconductor layer, a memory stack over the semiconductor layer, first channel structures each extending vertically through the memory stack in an edge region, and an isolation structure. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. At least one of conductive layers toward the semiconductor layer is a source select gate line (SSG). The isolation structure extends vertically through the SSG and into the semiconductor layer. The memory stack includes a core array region, a staircase region, and the edge region being laterally between the core array region and the staircase region. At least one of the first channel structures extends through the isolation structure and is separated from the SSG through the isolation structure.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.

Abstract: A method of fabricating a three-dimensional memory includes forming a laminated structure including stacked dummy gate layers and interlayer insulation layers on one side of a substrate. The respective adjacent dummy gate layers and interlayer insulation layers form staircase stairs. At least a part of the interlayer insulation layer of each of the staircase stairs is exposed. The method also includes forming a buffer layer covering the staircase stairs. The method further includes removing a part of the buffer layer covering the sidewalls of the staircase stairs to form spacing grooves. The method further includes forming a dielectric layer that fills the spacing grooves and covers the staircase stairs. The method further includes forming a contact hole penetrating through the dielectric layer and the buffer layer and extending to the dummy gate layer farthest from the substrate.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a memory stack having a plurality of stairs. Each stair may include interleaved one or more conductor layers and one or more dielectric layers. Each of the stairs includes one of the conductor layers on a top surface of the stair, the one of the conductor layers having (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion exposed by the memory stack and in contact with the bottom portion. A lateral dimension of the top portion may be less than a lateral dimension of the bottom portion. An end of the top portion that may be facing away from the memory stack laterally exceeds the bottom portion by a distance.