Abstract: A data processing apparatus includes a first chip and a second chip that are stacked-packaged. The first chip includes a general-purpose processor, a bus, and at least one first dedicated processing unit (DPU). The general-purpose processor and the at least one first dedicated processing unit are connected to the bus. The general-purpose processor is configured to generate a data processing task. The second chip includes a second dedicated processing unit. At least one of one or more units in the at least one first dedicated processing unit and the second dedicated processing unit can process at least a part of the data processing task based on a computing function.

Abstract: A terminal includes a security subsystem, a baseband processor, and a first bidirectional bus coupled between the security subsystem and the baseband processor. The security subsystem is configured to manage at least one of data related to a user identity or data related to network security in wireless communication, and exchange the data with the baseband processor by using the first bidirectional bus. The baseband processor is configured to exchange the data with the security subsystem by using the first bidirectional bus, and implement wireless communication by using the data. The security subsystem and the baseband processor are in the same hierarchy. The security subsystem may proactively perform data transmission by using the first bidirectional bus.

Abstract: A terminal includes a security subsystem, a baseband processor, and a first bidirectional bus coupled between the security subsystem and the baseband processor. The security subsystem is configured to manage at least one of data related to a user identity and data related to network security in wireless communication, and exchange the data with the baseband processor by using the first bidirectional bus. The baseband processor is configured to exchange the data with the security subsystem by using the first bidirectional bus, and implement wireless communication by using the data. The security subsystem and the baseband processor are in the same hierarchy. The security subsystem may proactively perform data transmission by using the first bidirectional bus.

Abstract: A data protection circuit of a chip, a chip, and an electronic device, where the data protection circuit performs bit width expansion and scrambling processing on a first alarm signal using an operation circuit to obtain a second alarm signal, and outputs the second alarm signal to a processing circuit. The processing circuit performs descrambling processing after receiving the second alarm signal to obtain a descrambling result. When the second alarm signal is attacked, the descrambling fails, and the descrambling result is an active level. The processing circuit outputs the descrambling result to a reset request circuit, and the reset request circuit generates a reset request signal according to the descrambling result.

Abstract: A system includes at least two buses including a first bus and a second bus, an encryption and decryption system corresponding to each bus, at least one signal processing module corresponding to each bus, and a bus converter coupled between the first bus and the second bus. According to the system provided in embodiments of the present invention, because data transmitted on a bus is encrypted data, even though an attacker obtains bus data by means of a probe attack, it is quite difficult to break a key, and an anti-attack capability of the system can be improved.

Abstract: A chip, including a selector, a one-time programmable (OTP) device, and a controller, where the controller is separately coupled to a selection end of the selector and the OTP device, and the controller is configured to detect a device value of the OTP device, and provide a first selection signal when the device value of the OTP device is within a first preset range. A first input end of the selector is configured to receive access data, a second input end of the selector is configured to receive a preset invalid value, and an output end of the selector is coupled to the OTP device. The selector is configured to control the data received by the second input end to be output from the output end of the selector when the first selection signal is input.

Abstract: A terminal includes a security subsystem, a baseband processor, and a first bidirectional bus coupled between the security subsystem and the baseband processor. The security subsystem is configured to manage at least one of data related to a user identity and data related to network security in wireless communication, and exchange the data with the baseband processor by using the first bidirectional bus. The baseband processor is configured to exchange the data with the security subsystem by using the first bidirectional bus, and implement wireless communication by using the data. The security subsystem and the baseband processor are in the same position. The security subsystem may proactively perform data transmission by using the first bidirectional bus.

Abstract: Embodiments of the present application disclose an operation method. The method includes: obtaining, by the input/output interface, an input ciphertext; performing, by the decryption circuit, a modular exponentiation operation according to the ciphertext and a preset operation parameter; and using, by the microprocessor, an operation result obtained after the modular exponentiation operation as a plaintext obtained after decryption.

Abstract: A data protection circuit of a chip, a chip, and an electronic device, where the data protection circuit performs bit width expansion and scrambling processing on a first alarm signal using an operation circuit to obtain a second alarm signal, and outputs the second alarm signal to a processing circuit. The processing circuit performs descrambling processing after receiving the second alarm signal to obtain a descrambling result. When the second alarm signal is attacked, the descrambling fails, and the descrambling result is an active level. The processing circuit outputs the descrambling result to a reset request circuit, and the reset request circuit generates a reset request signal according to the descrambling result.

Abstract: Embodiments of the present application disclose an operation method. The method includes: obtaining, by the input/output interface, an input ciphertext; performing, by the decryption circuit, a modular exponentiation operation according to the ciphertext and a preset operation parameter; and using, by the microprocessor, an operation result obtained after the modular exponentiation operation as a plaintext obtained after decryption.

Abstract: A system on chip is integrated on a first semiconductor chip, and includes: a system bus, at least one processor coupled to the system bus, and a security processor system coupled to the system bus. The security processor system includes a security processor, a first memory, multiple interfaces, and a security bus, where the security processor, the first memory, and the multiple interfaces are coupled to the security bus, and the security bus is coupled to the system bus. The security processor is configured to execute security operating system software and at least one security software application based on the security operating system software, where the at least one security software application includes mobile payment software used to implement mobile payment. The multiple interfaces include a near field communication (NFC) interface and a biometric recognition input interface.

Abstract: This application relates to the field of communications technologies, and discloses a mobile payment method. The method is applied to a system on chip SOC, where the SOC includes a secure element SE integrated into the SOC, and the method includes: receiving, by the SE, a transaction request; obtaining, by the SE, a first check value from an external memory; performing a security check on the external memory according to the first check value and a second check value that is stored locally in the SOC; and if the external memory passes the security check, obtaining, by the SE, first transaction data from the external memory, and processing the transaction request based on the first transaction data. This application is applied to a mobile payment process.

Abstract: A system includes at least two buses including a first bus and a second bus, an encryption and decryption system corresponding to each bus, at least one signal processing module corresponding to each bus, and a bus converter coupled between the first bus and the second bus. According to the system provided in embodiments of the present invention, because data transmitted on a bus is encrypted data, even though an attacker obtains bus data by means of a probe attack, it is quite difficult to break a key, and an anti-attack capability of the system can be improved.

Abstract: A chip, including a selector, a one-time programmable (OTP) device, and a controller, where the controller is separately coupled to a selection end of the selector and the OTP device, and the controller is configured to detect a device value of the OTP device, and provide a first selection signal when the device value of the OTP device is within a first preset range. A first input end of the selector is configured to receive access data, a second input end of the selector is configured to receive a preset invalid value, and an output end of the selector is coupled to the OTP device. The selector is configured to control the data received by the second input end to be output from the output end of the selector when the first selection signal is input.