Abstract: Embodiments of the present disclosure provide an array substrate, a display panel, and a display apparatus. The array substrate includes: a display region for displaying an image; a non-display region; a shift register provided in the non-display region; a gate line provided in the display region and extending along a first direction; and a gate signal output line, provided in the non-display region and having a first end and a second end. The first end of the gate signal output line is connected to the shift register, and the second end of the gate signal output line is connected to the gate line at a side of the gate line in a second direction perpendicular to the first direction.

Abstract: An array substrate includes: a base substrate, a gate line extending in a first direction, a data line extending in a second direction, and a pixel electrode layer, the first direction being substantially perpendicular to the second direction, the gate line and the data line defining a plurality of sub-pixel units, and a plurality of first and second common electrode lines electrically connected to each other and disposed in the same layer as the gate lines. The first common electrode line includes two first common electrode line first portions, and the second common electrode line extends in the second direction. The second common electrode line is located between and electrically connects the two first common electrode line first portions. The second common electrode line is located at a center line of the sub-pixel unit.

Abstract: Embodiments of the present disclosure provide an array substrate, a display panel, and a display apparatus. The array substrate includes: a display region for displaying an image; a non-display region; a shift register provided in the non-display region; a gate line provided in the display region and extending along a first direction; and a gate signal output line, provided in the non-display region and having a first end and a second end. The first end of the gate signal output line is connected to the shift register, and the second end of the gate signal output line is connected to the gate line at a side of the gate line in a second direction perpendicular to the first direction.

Abstract: A shift register includes a pull-up control circuit, a pull-up circuit, a pull-down control circuit, a pull-down circuit, and a reset circuit. The pull-down circuit is connected to the pull-down node, the pull-up node, a second control terminal, a first voltage terminal, and a signal output terminal, and is configured to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under the control of the pull-down node; moreover, the pull-down circuit is further configured to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under the control of a signal from the second control terminal.

Abstract: An array substrate includes: a base substrate, a gate line extending in a first direction, a data line extending in a second direction, and a pixel electrode layer, the first direction being substantially perpendicular to the second direction, the gate line and the data line defining a plurality of sub-pixel units, and a plurality of first and second common electrode lines electrically connected to each other and disposed in the same layer as the gate lines. The first common electrode line includes two first common electrode line first portions, and the second common electrode line extends in the second direction. The second common electrode line is located between and electrically connects the two first common electrode line first portions. The second common electrode line is located at a center line of the sub-pixel unit.

Abstract: A shift register includes a pull-up control circuit, a pull-up circuit, a pull-down control circuit, a pull-down circuit, and a reset circuit. The pull-down circuit is connected to the pull-down node, the pull-up node, a second control terminal, a first voltage terminal, and a signal output terminal, and is configured to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under the control of the pull-down node; moreover, the pull-down circuit is further configured to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under the control of a signal from the second control terminal.

Abstract: Embodiments of the present disclosure provide an array substrate, a method of manufacturing the same, a liquid crystal display panel, and a display device. The array substrate includes: a base substrate, a data line disposed on the base substrate and a pixel electrode layer disposed on a layer in which the data line is located. The pixel electrode layer includes a plurality of columns of pixel electrodes that are spaced apart from one another. An orthographic projection of the data line on the base substrate covers an orthographic projection of a gap between two adjacent columns of pixel electrodes on the base substrate, and a width of the data line is greater than a width of the gap between two adjacent columns of pixel electrodes.