Patents by Inventor Zhuofan CHEN

Zhuofan CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12178072
    Abstract: A display device is provided. A boundary of a projection of a first opening on a substrate is located between an inscribed circle and a circumscribed circle of a boundary of a projection of a corresponding subpixel on the substrate, so that the first opening cannot completely cover the corresponding subpixel. In this way, a light condensing effect in a non-planar display area is reduced, a bad experience with certain viewing angles in conventional non-planar display areas for users is improved, and user experience is enhanced.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: December 24, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Zhuofan Chen
  • Publication number: 20240057456
    Abstract: A display device is provided. In per unit area of the display device, a light-concentrating intensity of light emitted from sub-pixels in a non-planar display area and passing through a first optical film layer and a second optical film layer at a front viewing angle is less than a light-concentrating intensity of light emitted from the sub-pixels in a planar display area and passing through the first optical film layer and the second optical film layer at the front viewing angle. Poor user experiences at a certain viewing angle in the non-planar display area can be improved.
    Type: Application
    Filed: March 9, 2022
    Publication date: February 15, 2024
    Applicant: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Zhuofan Chen
  • Publication number: 20240049549
    Abstract: The present application provides a display panel, including: a substrate; a light emitting layer disposed on one side of the substrate and including a plurality of sub-pixels; a first optical layer disposed on one side of the light emitting layer away from the substrate and including a plurality of openings disposed corresponding to the sub-pixels; a second optical layer disposed on one side of the first optical layer away from the substrate and filling the openings, the second optical layer having a larger refractive index than the first optical layer; in the first row of sub-pixels, first gaps between sub-pixels and openings corresponding thereto in a first direction are larger than second gaps in a second direction different from first direction; and in the second row of sub-pixels, third gaps between sub-pixels and openings corresponding thereto in the first direction are smaller than fourth gaps in the second direction.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 8, 2024
    Applicant: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Zhuofan CHEN, Haoran WANG
  • Publication number: 20230292483
    Abstract: A semiconductor structure and its fabrication method are provided. The semiconductor structure includes: a substrate including a base substrate with a first device region and a second device region; a first active region on the first device region and a second active region on the second device region; an isolation layer between the first active region and the second active region; and a first gate electrode and a second gate electrode on the substrate. The first active region includes a first functional region and a first shared region. The first gate electrode is located on the device region and on a portion of a surface of the first active region. The second gate electrode is located on the second device region and on a portion of a surface of the second active region; and the second gate electrode also extends to a surface of the first shared area.
    Type: Application
    Filed: March 8, 2023
    Publication date: September 14, 2023
    Inventors: Zhuofan CHEN, Jisong JIN
  • Publication number: 20230276655
    Abstract: A display device is provided. A boundary of a projection of a first opening on a substrate is located between an inscribed circle and a circumscribed circle of a boundary of a projection of a corresponding subpixel on the substrate, so that the first opening cannot completely cover the corresponding subpixel. In this way, a light condensing effect in a non-planar display area is reduced, a bad experience with certain viewing angles in conventional non-planar display areas for users is improved, and user experience is enhanced.
    Type: Application
    Filed: March 3, 2022
    Publication date: August 31, 2023
    Inventor: Zhuofan CHEN
  • Patent number: 11276698
    Abstract: A flash memory device and its manufacturing method, which is related to semiconductor techniques. The flash memory device comprises: a substrate; and a memory unit on the substrate, comprising: a channel structure on the substrate, wherein the channel structure comprise, in an order from inner to outer of the channel structure, a channel layer, an insulation layer wrapped around the channel layer, and a charge capture layer wrapped around the insulation layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure, wherein there exist cavities between neighboring gate structures; a support structure supporting the gate structures; and a plurality of gate contact components each contacting a gate structure. The cavities between neighboring gate structures lower the parasitic capacitance, reduce inter-gate interference, and suppress the influence from writing or erasing operations of nearby memory units.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: March 15, 2022
    Inventors: Rongyao Chang, Zhuofan Chen, Haiyang Zhang
  • Patent number: 11257863
    Abstract: A magnetic random access memory includes a memory cell including a first fixed layer, a second fixed layer, and one or more free layers disposed between the first fixed layer and the second fixed layer. The first and second fixed layers are continuous layers and commonly shared by a plurality of memory cells. The magnetic random access memory has a relatively simple structure that not only reduces magnetic interference between memory cells, but also simplifies the fabrication process and increases the integration level.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: February 22, 2022
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Yibin Song, Zhuofan Chen
  • Patent number: 11069792
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: July 20, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Zhuofan Chen, Haiyang Zhang
  • Patent number: 11062952
    Abstract: The present disclosure provides a semiconductor structure and a forming method thereof. The forming method includes forming sacrificial layers and spacer on a dielectric layer, wherein the sacrificial layers and the spacer cover the dielectric layer at the top of a gate and expose the dielectric layer on at least part of source-drain doping layers, the sacrificial layers include the first sacrificial layer located on the dielectric layer at the top of the gate, and side walls of the first sacrificial layer are provided with the spacer; after the sacrificial layers and the spacer is formed, the first sacrificial layer is removed; and the dielectric layer is etched with a patterning layer as a mask, and a first contact hole and second contact holes are formed in the dielectric layer. The embodiments and implementations of the present disclosure can avoid double graphics of the dielectric layer and the alignment error.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: July 13, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Zhuofan Chen, Haiyang Zhang
  • Publication number: 20210183706
    Abstract: The present disclosure provides a semiconductor structure and a forming method thereof. The forming method includes forming sacrificial layers and spacer on a dielectric layer, wherein the sacrificial layers and the spacer cover the dielectric layer at the top of a gate and expose the dielectric layer on at least part of source-drain doping layers, the sacrificial layers include the first sacrificial layer located on the dielectric layer at the top of the gate, and side walls of the first sacrificial layer are provided with the spacer; after the sacrificial layers and the spacer is formed, the first sacrificial layer is removed; and the dielectric layer is etched with a patterning layer as a mask, and a first contact hole and second contact holes are formed in the dielectric layer. The embodiments and implementations of the present disclosure can avoid double graphics of the dielectric layer and the alignment error.
    Type: Application
    Filed: April 29, 2020
    Publication date: June 17, 2021
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhuofan CHEN, Haiyang ZHANG
  • Publication number: 20200251337
    Abstract: A semiconductor structure and a method for forming the same are provided.
    Type: Application
    Filed: October 15, 2019
    Publication date: August 6, 2020
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhuofan Chen, Haiyang Zhang
  • Patent number: 10714343
    Abstract: A semiconductor structure and a method for forming the same are provided.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 14, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Zhuofan Chen, Haiyang Zhang
  • Publication number: 20200105907
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhuofan CHEN, Haiyang ZHANG
  • Patent number: 10522651
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 31, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corp., Semiconductor Manufacturing International (Beijing) Corp.
    Inventors: Zhuofan Chen, Haiyang Zhang
  • Publication number: 20190363097
    Abstract: A flash memory device and its manufacturing method, which is related to semiconductor techniques. The flash memory device comprises: a substrate; and a memory unit on the substrate, comprising: a channel structure on the substrate, wherein the channel structure comprise, in an order from inner to outer of the channel structure, a channel layer, an insulation layer wrapped around the channel layer, and a charge capture layer wrapped around the insulation layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure, wherein there exist cavities between neighboring gate structures; a support structure supporting the gate structures; and a plurality of gate contact components each contacting a gate structure. The cavities between neighboring gate structures lower the parasitic capacitance, reduce inter-gate interference, and suppress the influence from writing or erasing operations of nearby memory units.
    Type: Application
    Filed: August 8, 2019
    Publication date: November 28, 2019
    Inventors: Rongyao CHANG, Zhuofan CHEN, Haiyang ZHANG
  • Patent number: 10388697
    Abstract: A magnetic random access memory and its manufacturing method related to semiconductor techniques. The magnetic random access memory comprises a word line, a bit line, and a memory unit positioned between the word line and the bit line, wherein the memory unit comprises a fixture layer connecting the bit line, a free layer connecting the word line, and an insulation layer positioned between the fixture layer and the free layer. This magnetic random access memory has a simpler design than conventional devices and can be manufactured more easily, which improves the integrity of the manufacturing process.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 20, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Zhuofan Chen, Yibin Song, Haiyang Zhang
  • Publication number: 20180286917
    Abstract: A magnetic random access memory includes a memory cell including a first fixed layer, a second fixed layer, and one or more free layers disposed between the first fixed layer and the second fixed layer. The first and second fixed layers are continuous layers and commonly shared by a plurality of memory cells. The magnetic random access memory has a relatively simple structure that not only reduces magnetic interference between memory cells, but also simplifies the fabrication process and increases the integration level.
    Type: Application
    Filed: February 15, 2018
    Publication date: October 4, 2018
    Inventors: Yibin Song, Zhuofan Chen
  • Publication number: 20180277755
    Abstract: A semiconductor device includes one or more bit lines, first and second select gates on the one or more bit lines, a plurality of word lines on the one or more bit lines and between the first and second select gates, and a source and a plurality of drains on the one or more bit lines. The source is disposed at an outside of the first select gate, and the plurality of drains are disposed at an outside of the second select gate. The semiconductor device based on electron tunneling effects includes only the source, drains and contacts disposed outside of the first and second select gates, without having a source, drain and contacts on opposite sides of each select gate, thereby increasing the memory density and the speed of write and erase operations.
    Type: Application
    Filed: February 28, 2018
    Publication date: September 27, 2018
    Inventors: ZHUOFAN CHEN, PANPAN LIU
  • Publication number: 20180158928
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer.
    Type: Application
    Filed: November 27, 2017
    Publication date: June 7, 2018
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhuofan Chen, Haiyang Zhang
  • Publication number: 20180122855
    Abstract: A magnetic random access memory and its manufacturing method related to semiconductor techniques. The magnetic random access memory comprises a word line, a bit line, and a memory unit positioned between the word line and the bit line, wherein the memory unit comprises a fixture layer connecting the bit line, a free layer connecting the word line, and an insulation layer positioned between the fixture layer and the free layer. This magnetic random access memory has a simpler design than conventional devices and can be manufactured more easily, which improves the integrity of the manufacturing process.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 3, 2018
    Inventors: Zhuofan CHEN, Yibin SONG, Haiyang ZHANG