Patents by Inventor Zhuojie Wu
Zhuojie Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154384Abstract: Structures for a cavity-mounted chip and methods of fabricating a structure for a cavity-mounted chip. The structure comprises a laser chip including a body attached to a substrate. The laser chip has an output, and the body of the laser chip has a bottom surface spaced from the substrate by a gap. The structure further comprises a first adhesive in the first gap and a second adhesive positioned in the first gap between the first adhesive and the output of the laser chip. The first adhesive has a first thermal conductivity, the second adhesive has a second thermal conductivity, and the first thermal conductivity of the first adhesive is greater than the second thermal conductivity of the second adhesive.Type: ApplicationFiled: November 8, 2022Publication date: May 9, 2024Inventors: Zhuojie Wu, Koushik Ramachandran, Yusheng Bian
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Publication number: 20240103237Abstract: A photonic integrated circuit (PIC) structure includes a substrate, and a cavity defined in the substrate, the cavity including a shoulder at a side of the cavity. A plurality of z-stop supports for an optical device are also included. Each z-stop support of the plurality of z-stop supports is on a support portion of the shoulder. A wire extends over the side of the cavity and between at least two z-stop supports of the plurality of z-stop supports. An optical device is positioned on the plurality of z-stop supports in the cavity and electrically coupled to the wire. Electrical connections between z-stop supports allows larger sized electrical connections to the optical device to mitigate electromigration issues, and increased options for electrical connections.Type: ApplicationFiled: September 19, 2022Publication date: March 28, 2024Inventors: Zhuojie Wu, Seungman Choi
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Publication number: 20240094465Abstract: The disclosure relates to a PIC structure including a photonic component on a semiconductor substrate. Each of a plurality of optical guard elements are composed of a light absorbing material and are in proximity to the photonic component. The optical guard elements may mimic an outer periphery of at least a portion of the photonic component. The optical guard elements may include at least one of: a germanium body positioned at least partially in a silicon element, a silicon body having a high dopant concentration, and a polysilicon body having a high dopant concentration over the silicon body.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Inventors: Yusheng Bian, Mark D. Levy, Siva P. Adusumilli, Karen A. Nummy, Zhuojie Wu, Ramsey Hazbun
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Publication number: 20240079371Abstract: The present disclosure relates to radio frequency (RF) chip packages and, more particularly, to improved thermal performance of RF chip packages and methods of manufacture. The structure includes: a board; a chip substrate; a pattern of solder bumps between the board and the chip substrate; and a thermal conductive material between the chip substrate and the board in depopulated regions of solder bumps of the chip substrate.Type: ApplicationFiled: September 2, 2022Publication date: March 7, 2024Inventors: John C. MALINOWSKI, Zhuojie WU
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Publication number: 20240077445Abstract: An integrated circuit (IC) structure includes a moisture barrier about active circuitry. A capacitor is entirely inside the moisture barrier. The capacitor has a breakdown voltage. A moisture detector is configured to apply an increasing voltage ramp to the capacitor up to a maximum voltage less than the breakdown voltage of the capacitor. In response to determining that a current hump exists in a test current-voltage response curve of the capacitor to the increasing voltage ramp, the detector transmits a signal to the active circuitry to indicate a presence of moisture in the IC structure. The moisture detector is accurate and sensitive to moisture ingress, which provides more time for remedial action. The detector is non-destructive and can be used in a final IC product.Type: ApplicationFiled: September 2, 2022Publication date: March 7, 2024Inventor: Zhuojie Wu
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Publication number: 20240019651Abstract: Disclosed is a photonic integrated circuit (PIC) structure including a scattering light-based monitor with photodetectors (e.g., PIN and/or avalanche photodiodes) placed adjacent to one or both sides of an end portion (i.e., a coupler) of a waveguide core at an optical interface with another optical device. The photodetectors are placed in such a way as to enable sensing of scattering light emitted from the end portion as light signals are received (e.g., either from the optical device for propagation to the main body of the waveguide core or from the main body for transmission to the optical device). Also disclosed are a monitoring system and method including the PIC chip structure with the above-described scattering light-based monitor. The system and method assess the optical interface using electric signals generated by the photodetectors.Type: ApplicationFiled: July 12, 2022Publication date: January 18, 2024Inventors: Zhuojie Wu, Yusheng Bian
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Publication number: 20230408763Abstract: The disclosure relates to a PIC structure including a photonic component on a semiconductor substrate. A passive optical guard is composed of a light absorbing material and is in proximity to the photonic component. The passive optical guard includes at least a portion in an active semiconductor layer of the semiconductor substrate and may be entirely below a first metal layer. The passive optical guard may include at least one of: a germanium body positioned at least partially in a silicon element in the active semiconductor layer, a silicon body having a high dopant concentration in the active semiconductor layer, and a polysilicon body having a high dopant concentration over the silicon body.Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Inventors: Zhuojie Wu, Yusheng Bian, Andreas D. Stricker
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Patent number: 11810870Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a moisture seal for photonic devices and methods of manufacture. The structure includes: a first trench in at least one substrate material; a guard ring structure with an opening and which at least partially surrounds the first trench; and a second trench at a dicing edge of the substrate, the second trench being lined on sidewalls with barrier material and spacer material over the barrier material.Type: GrantFiled: December 23, 2022Date of Patent: November 7, 2023Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Asli Sahin, Thomas F. Houghton, Jennifer A. Oakley, Jeremy S. Alderman, Karen A. Nummy, Zhuojie Wu
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Publication number: 20230126719Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a moisture seal for photonic devices and methods of manufacture. The structure includes: a first trench in at least one substrate material; a guard ring structure with an opening and which at least partially surrounds the first trench; and a second trench at a dicing edge of the substrate, the second trench being lined on sidewalls with barrier material and spacer material over the barrier material.Type: ApplicationFiled: December 23, 2022Publication date: April 27, 2023Inventors: Asli SAHIN, Thomas F. HOUGHTON, Jennifer A. OAKLEY, Jeremy S. ALDERMAN, Karen A. NUMMY, Zhuojie WU
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Patent number: 11587888Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a moisture seal for photonic devices and methods of manufacture. The structure includes: a first trench in at least one substrate material; a guard ring structure with an opening and which at least partially surrounds the first trench; and a second trench at a dicing edge of the substrate, the second trench being lined on sidewalls with barrier material and spacer material over the barrier material.Type: GrantFiled: December 13, 2019Date of Patent: February 21, 2023Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Asli Sahin, Thomas F. Houghton, Jennifer A. Oakley, Jeremy S. Alderman, Karen A. Nummy, Zhuojie Wu
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Patent number: 11531172Abstract: Structures for a photonics chip, testing methods for a photonics chip, and methods of forming a structure for a photonics chip. A photonics chip includes a first waveguide, a second waveguide, an optical tap coupling the first waveguide to the second waveguide, and a photodetector coupled to the second waveguide. A laser is attached to the photonics chip. The laser is configured to generate laser light directed by the first waveguide to the optical tap.Type: GrantFiled: May 13, 2020Date of Patent: December 20, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Zhuojie Wu, Bo Peng
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Publication number: 20210356684Abstract: Structures for a photonics chip, testing methods for a photonics chip, and methods of forming a structure for a photonics chip. A photonics chip includes a first waveguide, a second waveguide, an optical tap coupling the first waveguide to the second waveguide, and a photodetector coupled to the second waveguide. A laser is attached to the photonics chip. The laser is configured to generate laser light directed by the first waveguide to the optical tap.Type: ApplicationFiled: May 13, 2020Publication date: November 18, 2021Inventors: Zhuojie Wu, Bo Peng
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Publication number: 20210183791Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a moisture seal for photonic devices and methods of manufacture. The structure includes: a first trench in at least one substrate material; a guard ring structure with an opening and which at least partially surrounds the first trench; and a second trench at a dicing edge of the substrate, the second trench being lined on sidewalls with barrier material and spacer material over the barrier material.Type: ApplicationFiled: December 13, 2019Publication date: June 17, 2021Inventors: Asli SAHIN, Thomas F. HOUGHTON, Jennifer A. OAKLEY, Jeremy S. ALDERMAN, Karen A. NUMMY, Zhuojie WU
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Patent number: 10770407Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.Type: GrantFiled: January 4, 2019Date of Patent: September 8, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Zhuojie Wu, Cathryn J. Christiansen, Erdem Kaltalioglu, Ping-Chuan Wang, Ronald G. Filippi, Jr., Eric D. Hunt-Schroeder, Nicholas A. Polomoff
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Publication number: 20200219826Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.Type: ApplicationFiled: January 4, 2019Publication date: July 9, 2020Inventors: Zhuojie Wu, Cathryn J. Christiansen, Erdem Kaltalioglu, Ping-Chuan Wang, Ronald G. Filippi, JR., Eric D. Hunt-Schroeder, Nicholas A. Polomoff
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Patent number: 9947602Abstract: A sensor for an integrated circuit (IC) structure is disclosed. The sensor includes a sensor layer in a layer of the IC structure, the sensor layer including: a first conductive structure disposed proximate a perimeter of the IC structure; and a second conductive structure disposed parallel to the first conductive structure and proximate the perimeter of the IC structure. The sensor also includes a set of interdigitating conductive elements including a first plurality of conductive elements electrically coupled to the first conductive structure interdigitating with a second plurality of conductive elements electrically coupled to the second conductive structure.Type: GrantFiled: August 15, 2016Date of Patent: April 17, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Zhuojie Wu, Erdem Kaltalioglu
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Publication number: 20180042549Abstract: A method of making an injectable or implantable active agent delivery device capable of delivering a diagnostic, therapeutic, and/or prophylactic agent to a desired targeted site having orifice(s) on the surface is disclosed herein providing unidirectional release of the agent at a controlled desirable rate. The agent may include, but is not limited to, drugs, proteins, peptides, biomarkers, bioanalytes, and/or genetic material. The technology of the invention is based on parallel processing to fabricate micro-holes on tubes employing photo-lithography and reactive ion etching techniques and also incorporates a simple molding method to form the micro-holes on flexible polymer tubes, including bio-degradable tubes. The parallel processing method of the instant invention is fast, economical and well suited for mass production. The developed device, due to its composite structure, has the ability to combine several release mechanisms, leading to zero-order release kinetics for most of the time.Type: ApplicationFiled: July 27, 2017Publication date: February 15, 2018Inventors: Paul S. HO, Salomon STAVCHANSKY, Phillip BOWMAN, Zhiquan LUO, Zhuojie WU, Ashish RASTOGI
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Publication number: 20180047648Abstract: A sensor for an integrated circuit (IC) structure is disclosed. The sensor includes a sensor layer in a layer of the IC structure, the sensor layer including: a first conductive structure disposed proximate a perimeter of the IC structure; and a second conductive structure disposed parallel to the first conductive structure and proximate the perimeter of the IC structure. The sensor also includes a set of interdigitating conductive elements including a first plurality of conductive elements electrically coupled to the first conductive structure interdigitating with a second plurality of conductive elements electrically coupled to the second conductive structure.Type: ApplicationFiled: August 15, 2016Publication date: February 15, 2018Inventors: Zhuojie Wu, Erdem Kaltalioglu
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Patent number: 9403675Abstract: The disclosure relates to a method for forming a nanoscale structure by forming a pattern on a selectively etched layer located on top of a substrate using lithography, wherein the pattern results a gap having sidewalls, performing RIE on the gap having sidewalls, wherein RIE results in the formation of a self-aligned mask on the bottom wall of the gap with unprotected regions on the bottom wall of the gap near the junctions with the sidewalls, and wet etching the gap having a self-aligned mask and unprotected regions to remove the substrate under the unprotected regions to form a nanoscale structure in the substrate. The disclosure also relates to a nanoscale structure array including a plurality of nanotrenches, nanochannels or nanofins having a width of 50 nm or less and an average variation in width of 5% or less along the entire length of each nanotrench, nanochannel or nanofin.Type: GrantFiled: August 22, 2014Date of Patent: August 2, 2016Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEMInventors: Paul S. Ho, Zhuojie Wu
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Publication number: 20160172457Abstract: The present disclosure relates to a method of fabricating a silicon nanowire having a width of 100 nm or less, especially 50 nm or less, by depositing a metal film on a silicon-containing layer, treating the metal film using a wet process to produce an interconnected metal network having gaps on the silicon-containing layer, and etching the silicon-containing layer with a metal-assisted etching process to form a silicon nanowire having a width of 100 nm or less, especially 50 nm or less.Type: ApplicationFiled: February 10, 2016Publication date: June 16, 2016Inventors: Paul S. Ho, Zhuojie Wu