Patents by Inventor Zhuona Ma

Zhuona Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240266393
    Abstract: A metasurface structure includes a substrate having a first region and a second region not overlapping with the first region; a first pillar element within the first region on the substrate; and a second pillar element within the second region on the substrate. The first pillar element has a first sectional profile and the second pillar element has a second sectional profile that is different from the first sectional profile. At least one of the first sectional profile and the second sectional profile is of a non-rectangular shape.
    Type: Application
    Filed: March 9, 2023
    Publication date: August 8, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: CHUNYUAN QI, XINGXING CHEN, ZHUONA MA, HUI LIU
  • Publication number: 20230343639
    Abstract: An etch stop detection structure and an etch stop detection method are provided. The etch stop detection structure includes a substrate, a first dielectric layer, a first stop layer, and a second dielectric layer. The substrate includes a device region and a detection region. The first dielectric layer is located on the substrate. The first stop layer is located on the first dielectric layer. The second dielectric layer is located on the first stop layer. There is a first air gap in the first dielectric layer and the first stop layer in the device region. There is a trench in the second dielectric layer in the detection region. The trench exposes the first stop layer. The etch stop detection structure can be used to detect the etch stop signal.
    Type: Application
    Filed: May 19, 2022
    Publication date: October 26, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Runshun Wang, Mengkai Zhu, Zhuona Ma, Hua-Kuo Lee
  • Patent number: 11417735
    Abstract: A method for fabricating a semiconductor device is provided. The method includes providing a substrate, having a cell region and a logic region and including a first conductive layer as a top layer, wherein shallow trench isolation (STI) structures are disposed in the substrate at cell region and the logic region. A first dry etching process is performed to preliminarily etch the first conductive layer and the STI structures at the cell region. A wet etching process is performed over the substrate to etch the STI structures down to a preserved height. A control gate stack is formed on the first conductive layer at the cell region. A second dry etching process is performed on a portion of the first conductive layer to form a floating gate under the control gate stack at the cell region and remove the first conductive layer at the logic region.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 16, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhuona Ma, Mengkai Zhu, Runshun Wang, Hua-Kuo Lee
  • Publication number: 20210305377
    Abstract: A method for fabricating a semiconductor device is provided. The method includes providing a substrate, having a cell region and a logic region and including a first conductive layer as a top layer, wherein shallow trench isolation (STI) structures are disposed in the substrate at cell region and the logic region. A first dry etching process is performed to preliminarily etch the first conductive layer and the STI structures at the cell region. A wet etching process is performed over the substrate to etch the STI structures down to a preserved height. A control gate stack is formed on the first conductive layer at the cell region. A second dry etching process is performed on a portion of the first conductive layer to form a floating gate under the control gate stack at the cell region and remove the first conductive layer at the logic region.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Applicant: United Microelectronics Corp.
    Inventors: ZHUONA MA, Mengkai Zhu, Runshun Wang, Hua-Kuo Lee
  • Publication number: 20210020696
    Abstract: The invention discloses a structure of a memory device. The structure includes a substrate, having a memory region and a logic region. A barrier layer is disposed on the substrate, covering the memory region and the logic region. A patterned inter-layer dielectric layer is disposed on the barrier layer only at the memory region. A first via structure is formed in the barrier layer and the patterned inter-layer dielectric layer at the memory region. A memory cell structure is disposed on the patterned inter-layer dielectric layer at the memory region, in contact with the first via structure. An interconnection structure is disposed on the barrier layer at the logic region.
    Type: Application
    Filed: August 12, 2019
    Publication date: January 21, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Runshun Wang, Mengkai Zhu, Zhuona Ma, Hua-Kuo Lee