Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

Abstract: A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

Abstract: A planar inductor device includes a ferrite body and a conductive pathway, The ferrite body extends around an opening in the ferrite body. The conductive pathway includes an input section, a current-splitting section, a coil section, a current-combining section, and an output section connected with each other, the input section extending toward the opening in the ferrite body. The current-splitting section includes a plurality of conductive coils joined with the conductive pathway and electrically disposed parallel to each other. The coil section includes the conductive coils helically wrapped around the ferrite body. The current-combining section includes the conductive coils joined with each other. The output section includes the joined conductive coils extending out of the ferrite body.

Abstract: A planar inductor device includes a ferrite body and a conductive pathway. The ferrite body extends around an opening in the ferrite body. The conductive pathway includes an input section, a current-splitting section, a coil section, a current-combining section, and an output section connected with each other, the input section extending toward the opening in the ferrite body. The current-splitting section includes a plurality of conductive coils joined with the conductive pathway and electrically disposed parallel to each other. The coil section includes the conductive coils helically wrapped around the ferrite body. The current-combining section includes the conductive coils joined with each other. The output section includes the joined conductive coils extending out of the ferrite body.