Abstract: A semiconductor device includes a clock gating circuit and a control circuit. The clock gating circuit outputs a gated clock signal based on a clock signal. Transitions of the clock signal are output in the gated clock signal in response to a clock enable signal having an enable value and are disabled from being output in the gated clock signal in response to the clock enable signal having a disable value. The control circuit includes a first portion that operates based on the clock signal. The first portion sets the clock enable signal to the disable value in response to a disable control and sets the clock enable signal to the enable value in response to a wakeup control. The control circuit includes a second portion that operates based on the gated clock signal. The second portion provides the disable control to the first portion during an operation.

Abstract: In certain aspects, a memory device includes an array of memory cells and a peripheral circuit. The array of memory cells includes a first memory cell and a second memory cell. The peripheral circuit includes a page buffer circuit and control logic. The page buffer circuit is coupled to the first and second memory cells, respectively, and includes a sense out (SO) node and a cache storage unit. The control logic is coupled to the page buffer and configured to suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell. The control logic is further configured to control the page buffer circuit to store suspended program information associated with a suspension of the program operation, and initiate the read operation on the second memory cell through the SO node and the cache storage unit.

Abstract: In certain aspects, a memory device includes an array of memory cells, including a first memory cell and a second memory cell, and a peripheral circuit. The peripheral circuit includes a page buffer circuit and control logic. The control logic is configured to suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell, control the page buffer circuit to release a sensing storage unit and a cache storage unit of the page buffer circuit from being occupied by a suspension of the program operation through a usage of a dynamic storage unit of the page buffer circuit during the suspension of the program operation, and initiate a read operation on the second memory cell using the sensing storage unit and the cache storage unit.

Abstract: A memory device includes N memory planes (N is an integer greater than 1), M asynchronous multi-plane independent (AMPI) read units (M is an integer smaller than or equal to N), a first microcontroller unit (MCU), and a multiplexing circuit coupled to the N memory planes, the first MCU, and the M AMPI read units. Each AMPI read unit is configured to provide an AMPI read control signal for a respective memory plane to control an AMPI read operation on the respective memory plane. The first MCU is configured to provide a non-AMPI read control signal for each memory plane to control a non-AMPI read operation on each memory plane. The multiplexing circuit is configured to, in a non-AMPI read operation, direct a non-AMPI read control signal to each memory plane from the first MCU, and in an AMPI read operation, direct each AMPI read control signal of M AMPI read control signals to the respective memory plane from the corresponding AMPI read unit.

Abstract: In certain aspects, a method for operating a memory device is disclosed. The memory device includes a plurality of memory planes. Whether an instruction is an asynchronous multi-plane independent (AMPI) read instruction or a non-AMPI read instruction is determined. In response to the instruction being an AMPI read instruction, an AMPI read control signal is generated based on the AMPI read instruction, and the AMPI read control signal is directed to a corresponding memory plane of the memory planes. In response to the instruction being a non-AMPI read instruction, a non-AMPI read control signal is generated based on the non-AMPI read instruction, and the non-AMPI read control signal is directed to each memory plane of the memory planes.

Abstract: In certain aspects, a method for operating a memory device is disclosed. The memory device includes memory planes and multiplexers (MUXs). Each MUX includes an output coupled to a respective one of the memory planes, a first input receiving a non-asynchronous multi-plane independent (AMPI) read control signal, and a second input receiving an AMPI read control signal. Whether an instruction is an AMPI read instruction or a non-AMPI read instruction is determined. In response to the instruction being an AMPI read instruction, an AMPI read control signal is generated based on the AMPI read instruction, and a corresponding MUX is controlled to enable outputting the AMPI read control signal from the second input to the corresponding memory plane.

Abstract: A memory device, a method for controlling the memory device, and a memory system are provided. The memory device includes a memory array comprising a plurality of memory planes, and a peripheral circuit configured to control the plurality of memory planes to perform asynchronous operations. The peripheral circuit comprises a plurality of state machines connected to a memory interface of the memory device. Each state machine is configured to associated with one or more assigned memory planes of the plurality of memory planes. Each state machine is further configure to receive, from the memory interface in parallel with other state machines, a corresponding sequence of control commands of the one or more assigned memory planes; and independently process the corresponding sequence of control commands to obtain control information of the one or more assigned memory planes.

Abstract: A flash memory device includes a plurality of memory planes each contains arrays of memory cells; a host interface for accessing the plurality of memory planes by an external host; and a controller connected to the plurality of memory planes via a memory interface and controlling the host interface for accessing the plurality of memory planes. The controller is configured to perform: receiving one or more commands on the host interface from the external host; determining whether to perform asynchronous multi-plane independent (AMPI) read operation corresponding to the commands; and after determining to start the AMPI read operation, accessing the memory planes in parallel according to the commands, and completing the AMPI read operation using an order of the commands determined based on an indicator signal provided to the controller to correspond to a sequence of the commands received on the host interface.

Abstract: A semiconductor device includes a clock gating circuit and a control circuit. The clock gating circuit outputs a gated clock signal based on a clock signal. Transitions of the clock signal are output in the gated clock signal in response to a clock enable signal having an enable value and are disabled from being output in the gated clock signal in response to the clock enable signal having a disable value. The control circuit includes a first portion that operates based on the clock signal. The first portion sets the clock enable signal to the disable value in response to a disable control and sets the clock enable signal to the enable value in response to a wakeup control. The control circuit includes a second portion that operates based on the gated clock signal. The second portion provides the disable control to the first portion during an operation.

Abstract: In certain aspects, a method for operating a memory device is disclosed. The memory device includes a plurality of memory planes. Whether an instruction is an asynchronous multi-plane independent (AMPI) read instruction or a non-AMPI read instruction is determined. In response to the instruction being an AMPI read instruction, an AMPI read control signal is generated based on the AMPI read instruction, and the AMPI read control signal is directed to a corresponding memory plane of the memory planes. In response to the instruction being a non-AMPI read instruction, a non-AMPI read control signal is generated based on the non-AMPI read instruction, and the non-AMPI read control signal is directed to each memory plane of the memory planes.

Abstract: In certain aspects, a method for operating a memory device is disclosed. The memory device includes memory planes and multiplexers (MUXs). Each MUX includes an output coupled to a respective one of the memory planes, a first input receiving a non-asynchronous multi-plane independent (AMPI) read control signal, and a second input receiving an AMPI read control signal. Whether an instruction is an AMPI read instruction or a non-AMPI read instruction is determined. In response to the instruction being an AMPI read instruction, an AMPI read control signal is generated based on the AMPI read instruction, and a corresponding MUX is controlled to enable outputting the AMPI read control signal from the second input to the corresponding memory plane.

Abstract: A flash memory device includes a plurality of memory planes each contains arrays of memory cells; a host interface for accessing the plurality of memory planes by an external host; and a controller connected to the plurality of memory planes via a memory interface and controlling the host interface for accessing the plurality of memory planes. The controller is configured to perform: receiving one or more commands on the host interface from the external host; determining whether to perform asynchronous multi-plane independent (AMPI) read operation corresponding to the commands; and after determining to start the AMPI read operation, accessing the memory planes in parallel according to the commands, and completing the AMPI read operation using an order of the commands determined based on an indicator signal provided to the controller to correspond to a sequence of the commands received on the host interface.