Patents by Inventor Zi-Ang Su
Zi-Ang Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240145466Abstract: Bipolar junction transistors (BJTs) are disclosed that are formed on a superlattice structure of stacked silicon and silicon germanium layers. The superlattice structure can be implanted with ions to form emitter, base, and collector regions of the BJTs. Altering width ratios of the implanted emitter, base, and collector regions can tune BJT performance. The BJTs can be implemented in a Darlington circuit configuration.Type: ApplicationFiled: March 20, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Zi-Ang SU
-
Patent number: 11948936Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.Type: GrantFiled: April 24, 2023Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hung Wang, Chih Chieh Yeh, Zi-Ang Su, Chia-Ju Chou, Ming-Shuan Li
-
Publication number: 20240055424Abstract: A semiconductor structure includes a substrate and a stack of p-n junction structures embedded in the substrate. The semiconductor structure includes a semiconductor fin protruding from the substrate. The semiconductor structure includes a pair of source/drain structures disposed in the semiconductor fin. The semiconductor structure includes a gate structure over a channel region of the semiconductor fin and interposed between the pair of source/drain structures.Type: ApplicationFiled: February 7, 2023Publication date: February 15, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chung Chen, Zi-Ang Su, Bo-Ting Chen, Chung-Sheng Yuan, Yi-Kan Cheng
-
Publication number: 20240014290Abstract: A semiconductor structure includes a first semiconductor layer having an upper portion over a lower portion, a source/drain feature over the upper portion of the first semiconductor layer, a first contact structure under the lower portion of the first semiconductor layer and electrically connected to the lower portion of the first semiconductor layer. The lower portion is more heavily doped with first dopants than the upper portion. The first dopants are of a first conductivity-type. The source/drain feature includes second dopants of a second conductivity-type opposite to the first conductivity-type.Type: ApplicationFiled: August 9, 2023Publication date: January 11, 2024Inventors: Chih Chieh Yeh, Ming-Shuan Li, Chih-Hung Wang, Zi-Ang Su
-
Patent number: 11843038Abstract: Embodiments include a first set of fins having an emitter of a bipolar junction transistor (BJT) disposed over the first set of fins, a second set of fins having a base of the BJT disposed over the second set of fins, and a third set of fins having a collector of the BJT disposed over the third set of fins. A first gate structure is disposed over the first set of fins adjacent to the emitter. A second gate structure is disposed over the second set of fins adjacent to the base. A third gate structure is disposed over the third set of fins adjacent to the collector. The first gate structure, second gate structure, and third gate structure are physically and electrically separated.Type: GrantFiled: January 31, 2022Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Shuan Li, Zi-Ang Su, Ying-Keung Leung
-
Patent number: 11837459Abstract: A method includes providing a first semiconductor layer at a frontside of a structure; implanting first dopants of a first conductivity-type into the first semiconductor layer, resulting in a doped layer in the first semiconductor layer; forming a stack of semiconductor layers over the first semiconductor layer; patterning the stack of semiconductor layers and the first semiconductor layer into fins; forming an isolation structure adjacent to a lower portion of the fins; etching the stack of semiconductor layers to form a source/drain trench over the first semiconductor layer; forming a source/drain feature in the source/drain trench, wherein the source/drain feature is doped with second dopants of a second conductivity-type opposite to the first conductivity-type; forming a contact hole at a backside of the structure, wherein the contact hole exposes the doped layer in the first semiconductor layer; and forming a first contact structure in the contact hole.Type: GrantFiled: August 31, 2021Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih Chieh Yeh, Ming-Shuan Li, Chih-Hung Wang, Zi-Ang Su
-
Patent number: 11830938Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.Type: GrantFiled: March 6, 2023Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zi-Ang Su, Chih Chieh Yeh, Ming-Shuan Li
-
Publication number: 20230378287Abstract: Embodiments include a first set of fins having an emitter of a bipolar junction transistor (BJT) disposed over the first set of fins, a second set of fins having a base of the BJT disposed over the second set of fins, and a third set of fins having a collector of the BJT disposed over the third set of fins. A first gate structure is disposed over the first set of fins adjacent to the emitter. A second gate structure is disposed over the second set of fins adjacent to the base. A third gate structure is disposed over the third set of fins adjacent to the collector. The first gate structure, second gate structure, and third gate structure are physically and electrically separated.Type: ApplicationFiled: August 8, 2023Publication date: November 23, 2023Inventors: Ming-Shuan Li, Zi-Ang Su, Ying-Keung Leung
-
Publication number: 20230282702Abstract: A semiconductor device includes a substrate. The semiconductor device includes a first gate region extending into the substrate and having at least a portion of a first U-shape. The semiconductor device includes a channel region extending into the substrate and having a second U-shape. The semiconductor device includes a second gate region extending into the substrate and having a well shape. The well shape is disposed between the second U-shape, and the second U-shape is disposed further between the first U-shape.Type: ApplicationFiled: June 27, 2022Publication date: September 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chung Chen, Zi-Ang Su, Ya Yun Liu, Yi-Kan Cheng
-
Publication number: 20230268337Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.Type: ApplicationFiled: April 24, 2023Publication date: August 24, 2023Inventors: Chih-Hung Wang, Chih Chieh Yeh, Zi-Ang Su, Chia-Ju Chou, Ming-Shuan Li
-
Publication number: 20230207671Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Inventors: Zi-Ang Su, Chih Chieh Yeh, Ming-Shuan Li
-
Patent number: 11637099Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a structure having a frontside and a backside, the structure including a substrate and a stack of a first type and a second type epitaxial layers having different material compositions alternatively stacked above the substrate, wherein the stack is at the frontside of the structure and the substrate is at the backside of the structure; patterning the stack, thereby forming a fin above the substrate; implanting a first dopant into a first region of the fin, the first dopant having a first conductivity type; implanting a second dopant into a second region of the fin, the second dopant having a second conductivity type opposite the first conductivity type; and forming a first contact on the first region and a second contact on the second region.Type: GrantFiled: April 7, 2021Date of Patent: April 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hung Wang, Ming-Shuan Li, Chih Chieh Yeh, Zi-Ang Su, Chia-Ju Chou
-
Patent number: 11600719Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.Type: GrantFiled: March 28, 2022Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zi-Ang Su, Ming-Shuan Li, Chih Chieh Yeh
-
Publication number: 20230069501Abstract: A method includes providing a first semiconductor layer at a frontside of a structure; implanting first dopants of a first conductivity-type into the first semiconductor layer, resulting in a doped layer in the first semiconductor layer; forming a stack of semiconductor layers over the first semiconductor layer; patterning the stack of semiconductor layers and the first semiconductor layer into fins; forming an isolation structure adjacent to a lower portion of the fins; etching the stack of semiconductor layers to form a source/drain trench over the first semiconductor layer; forming a source/drain feature in the source/drain trench, wherein the source/drain feature is doped with second dopants of a second conductivity-type opposite to the first conductivity-type; forming a contact hole at a backside of the structure, wherein the contact hole exposes the doped layer in the first semiconductor layer; and forming a first contact structure in the contact hole.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Chih Chieh Yeh, Ming-Shuan Li, Chih-Hung Wang, Zi-Ang Su
-
Publication number: 20220216330Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.Type: ApplicationFiled: March 28, 2022Publication date: July 7, 2022Inventors: Zi-Ang Su, Ming-Shuan Li, Chih Chieh Yeh
-
Publication number: 20220157953Abstract: Embodiments include a first set of fins having an emitter of a bipolar junction transistor (BJT) disposed over the first set of fins, a second set of fins having a base of the BJT disposed over the second set of fins, and a third set of fins having a collector of the BJT disposed over the third set of fins. A first gate structure is disposed over the first set of fins adjacent to the emitter. A second gate structure is disposed over the second set of fins adjacent to the base. A third gate structure is disposed over the third set of fins adjacent to the collector. The first gate structure, second gate structure, and third gate structure are physically and electrically separated.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Ming-Shuan Li, Zi-Ang Su, Ying-Keung Leung
-
Publication number: 20220113199Abstract: The present disclosure provides embodiments of semiconductor devices. In one embodiment, the semiconductor device includes a dielectric layer and a fin-shaped structure disposed over the dielectric layer. The fin-shaped structure includes a first p-type doped region, a second p-type doped region, and a third p-type doped region, and a first n-type doped region, a second n-type doped region, and a third n-type doped region interleaving the first p-type doped region, the second p-type doped region, and the third p-type doped region. The first p-type doped region, the third p-type doped region and the third n-type doped region are electrically coupled to a first potential. The second p-type doped region, the first p-type doped region and the second p-type doped region are electrically coupled to a second potential different from the first potential.Type: ApplicationFiled: October 13, 2020Publication date: April 14, 2022Inventors: Zi-Ang Su, Ming-Shuan Li, Shu-Hua Wu, Chih Chieh Yeh, Chih-Hung Wang, Wen-Hsing Hsieh
-
Publication number: 20220102537Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Inventors: Zi-Ang Su, Ming-Shuan Li, Chih Chieh Yeh
-
Patent number: 11289591Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.Type: GrantFiled: September 30, 2020Date of Patent: March 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zi-Ang Su, Ming-Shuan Li, Chih Chieh Yeh
-
Patent number: 11239330Abstract: Embodiments include a first set of fins having an emitter of a bipolar junction transistor (BJT) disposed over the first set of fins, a second set of fins having a base of the BJT disposed over the second set of fins, and a third set of fins having a collector of the BJT disposed over the third set of fins. A first gate structure is disposed over the first set of fins adjacent to the emitter. A second gate structure is disposed over the second set of fins adjacent to the base. A third gate structure is disposed over the third set of fins adjacent to the collector. The first gate structure, second gate structure, and third gate structure are physically and electrically separated.Type: GrantFiled: February 7, 2020Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Shuan Li, Zi-Ang Su, Ying-Keung Leung