Patents by Inventor Zi Song
Zi Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220274069Abstract: The present application discloses a conductive membrane and a preparation method thereof, which belong to the field of membrane separation technology. The conductive membrane provided by the present application includes a porous base layer film, a porous intermediate layer film, and a porous conductive layer film which are disposed layer by layer in sequence; wherein at least some holes of the base layer film are communicated with holes of the conductive layer film through holes of the intermediate layer film, and material of the intermediate layer film is the same as material of the base layer film and of the conductive layer film. Regarding the conductive membrane provided by the present application, it can be coupled with electrochemical technology, so that the membrane exhibits new excellent properties at the same time of playing separating characteristic.Type: ApplicationFiled: May 12, 2022Publication date: September 1, 2022Inventors: FEIYUN SUN, Jingyi Yang, Wenyi Dong, Lingyan Zhao, Dingyu Xing, Songwen Yang, Zi Song, Ji Li
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Publication number: 20220242989Abstract: Provided herein is a masterbatch including a grafted silicone polyether and a porous inorganic nanoparticle, bacteria repellant polymer composites including the same, and methods of preparation thereof.Type: ApplicationFiled: February 3, 2021Publication date: August 4, 2022Inventors: You WU, Ho-Man AU, Yan-Hua ZHAO, Hoi-Kuan KONG, Xi-Zi SONG, Wai-Chung, Peter WONG, Cheuk Nang, Daniel SUNG, Yuen-Fat LEE
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Publication number: 20220098359Abstract: Described herein is a polyurethane foam prepared with certain polytetrahydrofurans and optional polyether polyols. The polyurethane foam is characterized by low hardness increase at low temperature as compared with conventional polyurethane foam, and is suitable for use in products which can be exposed to low temperature such as snow boots.Type: ApplicationFiled: January 14, 2020Publication date: March 31, 2022Inventors: Bang Wei Xi, YingHao Liu, Zhen Peng Liang, Jin Lin Liu, Bo Chen, Ben Ben Shen, Zi Song Zhu
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Patent number: 10654709Abstract: A shielded semiconductor device is assembled using a lead frame having a die receiving area, leads disposed around the die receiving area, and a bendable strip formed in the die receiving area. Each lead has an inner lead end that is spaced from but near to one of the sides of the die receiving area and an outer lead end that is distal to that side of the die receiving area. An IC die is attached to the die receiving area and electrically connected to the inner lead ends of the leads. An encapsulant is formed over the die and the electrical connections and forms a body. The strip is bent to extend vertically to a top side of the body. A lid is formed on the top side of the body and is in contact with a distal end of the vertical strip.Type: GrantFiled: October 30, 2018Date of Patent: May 19, 2020Assignee: NXP USA, Inc.Inventors: Lee Fee Ngion, Zi-Song Poh, Michael B. Vincent
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Publication number: 20200131030Abstract: A shielded semiconductor device is assembled using a lead frame having a die receiving area, leads disposed around the die receiving area, and a bendable strip formed in the die receiving area. Each lead has an inner lead end that is spaced from but near to one of the sides of the die receiving area and an outer lead end that is distal to that side of the die receiving area. An IC die is attached to the die receiving area and electrically connected to the inner lead ends of the leads. An encapsulant is formed over the die and the electrical connections and forms a body. The strip is bent to extend vertically to a top side of the body. A lid is formed on the top side of the body and is in contact with a distal end of the vertical strip.Type: ApplicationFiled: October 30, 2018Publication date: April 30, 2020Inventors: Lee Fee Ngion, Zi-Song Poh, Michael B. Vincent
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Patent number: 9698093Abstract: A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different BGA package of a particular package size. The same substrate can be used to assemble BGA packages of different size, thereby avoiding having to design a different substrate for each different BGA package size.Type: GrantFiled: August 24, 2015Date of Patent: July 4, 2017Assignee: NXP USA,INC.Inventors: Chee Seng Foong, Ly Hoon Khoo, Wen Shi Koh, Wai Yew Lo, Zi Song Poh, Kai Yun Yow
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Publication number: 20170062320Abstract: A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different BGA package of a particular package size. The same substrate can be used to assemble BGA packages of different size, thereby avoiding having to design a different substrate for each different BGA package size.Type: ApplicationFiled: August 24, 2015Publication date: March 2, 2017Inventors: CHEE SENG FOONG, LY HOON KHOO, WEN SHI KOH, WAI YEW LO, ZI SONG POH, KAI YUN YOW
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Patent number: 9209144Abstract: A substrate for use in semiconductor device assembly has an electrically insulating body with a die mounting surface and an opposite grid array surface. An array of external electrical connection pads is located in the grid array surface. Substrate bond padsare located in the die mounting surface. Interconnects in the insulating body selectively interconnect the substrate bond padsto the external electrical connection pads. Tertiary bond pads are located in the die mounting surface and are electrically isolated from the external electrical connection pads.Type: GrantFiled: September 29, 2014Date of Patent: December 8, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Lee Fee Ngion, Zi Song Poh
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Patent number: 9209147Abstract: A method of forming a pillar bump includes feeding a bond wire in a capillary. The capillary has a hole portion and a chamfer section arranged downstream of the hole portion. The hole portion has a length along a feed direction of the bond wire that is greater than a maximum diameter of the hole portion. The method further includes performing an electric flame off (EFO) on a free end of the bond wire extending from the chamfer section to form a free air ball (FAB), tensioning the bond wire and applying a vacuum to the capillary to withdraw a portion of the FAB back into the capillary to substantially fill the hole portion for forming a tower, attaching the FAB to a bonding site, and at least partially removing the capillary from the bonding site and breaking the bond wire above the tower.Type: GrantFiled: July 17, 2014Date of Patent: December 8, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chee Seng Foong, Lee Fee Ngion, Navas Khan Oratti Kalandar, Zi Song Poh
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Publication number: 20150311143Abstract: A lead frame has a trace embedded in an encapsulant and a plurality of stubs (i) embedded in the encapsulant and (ii) connected to and extending from the trace at different locations along the length of the trace. The stubs inhibit the formation of cracks that may otherwise form along the trace due to thermal or mechanical bending of the lead frame, especially cracks that tend to occur along the four linear edge traces located at the periphery of some conventional embedded lead frames.Type: ApplicationFiled: April 29, 2014Publication date: October 29, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Chee Seng Foong, Boon Yew Low, Zi Song Poh
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Patent number: 9165904Abstract: A method of attaching a bond wire to first and second electrical contact pads includes holding the bond wire in a capillary, wherein a first end of the bond wire extends out of an opening in the capillary, attaching the first end of the bond wire to the first electrical contact pad using a ball bonding technique, moving a second end of the bond wire toward the second electrical contact pad after the attachment of the first end of the bond wire, performing an electric flame off on the second end of the bond wire without forming a free air ball, and attaching the second end of the bond wire to the second electrical contact pad after the EFO on the second end of the bond wire.Type: GrantFiled: June 17, 2014Date of Patent: October 20, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chin Teck Siong, Zi Song Poh, Lan Chu Tan
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Patent number: 8450841Abstract: A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.Type: GrantFiled: August 1, 2011Date of Patent: May 28, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Li Ting Celina Ong, Yin Kheng Au, Zi-Song Poh
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Publication number: 20130032932Abstract: A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.Type: ApplicationFiled: August 1, 2011Publication date: February 7, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Li Ting Celina ONG, Yin Kheng Au, Zi-Song Poh
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Publication number: 20110204498Abstract: A lead frame for a semiconductor package has a flag to which a semiconductor die is mounted. Tie bars are coupled to the flag. There is a first set of leads and each first set lead in the first set of leads has a first set lead parallel length and a first set lead tapered length. The first set lead parallel length of each first set lead has a constant width and edges that are parallel to edges of all other first set lead parallel lengths. A free end region of the first set lead tapered length of each first set lead provides a first set lead bond target region. There is a second set of leads disposed between a first one of the tie bars and the first set of leads. Each second set lead, in the second set of leads, has a second set lead parallel length and a second set lead tapered length.Type: ApplicationFiled: February 24, 2010Publication date: August 25, 2011Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Yin Kheng Au, Mohd Rusli Ibrahim, Meng Kong Lye, Zi Song Poh, Seng Kiong Teng, Kesyakumar V.C. Muniandy
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Patent number: 7341913Abstract: The invention is directed to a method for manufacturing a non-volatile memory. The method comprises steps of forming a mask layer on a substrate. An isolation structure is formed in the mask layer and the substrate, wherein the top surface of the isolation structure is lower than that of the mask layer and the isolation structure and the mask layer together form a recession. A spacer is formed at the sidewall of the recession and the recession is filled with an insulating layer. The mask layer and the spacer are removed and a tunneling dielectric layer is formed over the substrate. A first conductive layer is formed to fill the first opening and the isolating layer is removed to form a second opening. A gate dielectric layer and a second conductive layer are formed over the substrate sequentially. The second conductive layer and the first conductive layer are patterned.Type: GrantFiled: March 10, 2006Date of Patent: March 11, 2008Assignee: Powerchip Semiconductor Corp.Inventor: Zi-Song Wang
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Publication number: 20070148861Abstract: The invention is directed to a method for manufacturing a non-volatile memory. The method comprises steps of forming a mask layer on a substrate. An isolation structure is formed in the mask layer and the substrate, wherein the top surface of the isolation structure is lower than that of the mask layer and the isolation structure and the mask layer together form a recession. A spacer is formed at the sidewall of the recession and the recession is filled with an insulating layer. The mask layer and the spacer are removed and a tunneling dielectric layer is formed over the substrate. A first conductive layer is formed to fill the first opening and the isolating layer is removed to form a second opening. A gate dielectric layer and a second conductive layer are formed over the substrate sequentially. The second conductive layer and the first conductive layer are patterned.Type: ApplicationFiled: March 10, 2006Publication date: June 28, 2007Inventor: Zi-Song Wang