Abstract: A connector and a chamber are provided. The connector of the chamber includes the first sub connector, the second sub connector and the plurality of foldable connectors. Each wire can be covered by the connector and does not need to be exposed. The wire is protected and organized, and the appearance of the chamber is aesthetically pleasing. Moreover, when the chamber is in the close operation, the protrusion of each sub connector is disposed in the slide track of the former sub connector, and each sub connector is received in the accommodation space of the former sub connector, so that the requirement space of the connector is reduced and the volume of the chamber is reduced.

Abstract: A battery charging chamber is provided. The battery charging chamber charges or discharges a battery. The battery charging chamber includes a box, a cover and a connector. The box includes a first casing and a chassis. The chassis is disposed in a first accommodation space of the first casing for receiving the battery. The cover includes a second casing, a first plate, a second plate and an AC/DC conversion module. The first plate, the second plate and the AC/DC conversion module are disposed in a second accommodation space of the second casing. The first plate is made of metal and disposed between the second plate and a bottom of the second casing. The second plate includes a set of heat dissipation holes. The AC/DC conversion module is disposed between the second plate and the first plate. The box and the cover are pivotally connected with each other through the connector.

Abstract: A semiconductor device includes a semiconductor substrate, a first gate structure over the substrate, a second gate structure over the substrate, first gate spacers, second gate spacers, first and second metal layers spanning over the first and second gate structures, first and second contact plugs extending through the first and second metal layers, respectively. The first gate structure includes a first gate dielectric, and a first work function metal layer over the first gate dielectric. The second gate structure is wider than the first gate structure, wherein the second gate structure includes a second gate dielectric, a second work function metal layer over the second gate dielectric, and a filling conductor over the second work function metal layer. The first contact plug is in contact with the first work function metal layer, and the second contact plug is in contact with the filling conductor.

Abstract: A method includes forming a semiconductor fin; forming a gate dielectric layer over the semiconductor fin; depositing a first work function metal layer over the gate dielectric layer, the first work function metal layer having a first concentration of a work function material; depositing a second work function metal layer over the first work function metal layer, the second work function metal layer having a second concentration of the work function material, wherein the first concentration is higher than the second concentration; and forming a gate electrode over the second work function metal layer.

Abstract: A method includes following steps. A semiconductor fin is formed extending from a substrate. A gate dielectric layer is formed to wrap around semiconductor fin. A P-type work function layer is formed to wrap around the gate dielectric layer. An N-type work function layer is formed to wrap around the P-type work function layer. The N-type work function layer has a work function different from a work function of the P-type work function layer. The N-type work function layer is treated such that an upper portion of the N-type work function layer has a different composition than a lower portion of the N-type work function layer.

Abstract: A semiconductor device includes a silicon germanium channel, a germanium-free interfacial layer, a high-k dielectric layer, and a metal gate electrode. The silicon germanium channel is over a substrate. The germanium-free interfacial layer is over the silicon germanium channel. The germanium-free interfacial layer is nitridated. The high-k dielectric layer is over the germanium-free interfacial layer. The metal gate electrode is over the high-k dielectric layer.

Abstract: A robotic arm includes a first transmission module, a second transmission module, and a third transmission module. The first transmission module provides a first driven gear to connect with the second transmission module and provides a first fixed gear to engage with a first planetary gear of the second transmission module. When the second transmission module is driven by the first driven gear, the first planetary gear is rotated and revolved around the first fixed gear. The second transmission module uses a second driven gear to connect with the third transmission module connected with a surgical instrument. When driven by the second driven gear, the third transmission module drives the surgical instrument to act. As such, the robotic arm of the present invention is only equipped with a single actuator to achieve an effect of multi-arm linkage.

Abstract: A device includes a semiconductor channel region and a gate structure. The semiconductor channel region is on a substrate. The gate structure is over the semiconductor channel region and comprises a gate dielectric layer, a first gate conductor layer, and a second gate conductor layer. The first gate conductor layer is over the gate dielectric layer. The first gate conductor layer includes oxygen. The second gate conductor layer is over the first gate conductor layer.

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.

Abstract: A method for forming a semiconductor structure includes forming a gate structure on a substrate; depositing a first dielectric layer over the gate structure; depositing a second dielectric layer over the first dielectric layer and having a different density than the first dielectric layer; performing a first etching process on the first and second dielectric layers to form a trench; performing a second etching process on the first and second dielectric layers to modify the trench; filling a conductive material in the modified trench.

Abstract: A semiconductor device includes a semiconductor substrate, a first gate structure over the substrate, a second gate structure over the substrate, first gate spacers, second gate spacers, first and second metal layers spanning over the first and second gate structures, first and second contact plugs extending through the first and second metal layers, respectively. The first gate structure includes a first gate dielectric, and a first work function metal layer over the first gate dielectric. The second gate structure is wider than the first gate structure, wherein the second gate structure includes a second gate dielectric, a second work function metal layer over the second gate dielectric, and a filling conductor over the second work function metal layer. The first contact plug is in contact with the first work function metal layer, and the second contact plug is in contact with the filling conductor.

Abstract: A semiconductor device includes a semiconductor substrate, a first gate structure over the substrate, a second gate structure over the substrate, first gate spacers, second gate spacers, first and second metal layers spanning over the first and second gate structures, first and second contact plugs extending through the first and second metal layers, respectively. The first gate structure includes a first gate dielectric, and a first work function metal layer over the first gate dielectric. The second gate structure is wider than the first gate structure, wherein the second gate structure includes a second gate dielectric, a second work function metal layer over the second gate dielectric, and a filling conductor over the second work function metal layer. The first contact plug is in contact with the first work function metal layer, and the second contact plug is in contact with the filling conductor.

Abstract: Battery core packs employing specific electrolyte solutions and minimum cell-face pressures and methods are disclosed for minimizing dendrite growth and increasing cycle life of metal and metal-ion battery cells.

Abstract: A semiconductor device includes a substrate, a semiconductor fin extending from the substrate, a gate dielectric layer over the semiconductor fin, a metal nitride layer comprising a first portion over the gate dielectric layer and a second portion over the first portion, and a fill layer over the metal nitride layer. The second portion has an aluminum concentration greater than an aluminum concentration of the first portion.

Abstract: A device includes a substrate retainer for retaining a substrate thereon, and a ring assembly including an upper ring which has a plurality of upper ring segments that are angularly displaced from each other. Each of the upper ring segments is movable between an inner position and an outer position so as to adjust a gap between an outer periphery of the substrate and an inner edge of each of the upper ring segments when the substrate is retained on the substrate retainer.

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.

Abstract: A semiconductor device includes a silicon germanium channel, a germanium-free interfacial layer, a high-k dielectric layer, and a metal gate electrode. The silicon germanium channel is over a substrate. The germanium-free interfacial layer is over the silicon germanium channel. The germanium-free interfacial layer is nitridated. The high-k dielectric layer is over the germanium-free interfacial layer. The metal gate electrode is over the high-k dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin extending from the semiconductor substrate, a gate structure extending across the semiconductor fin, and source/drain semiconductor layers on opposite sides of the gate structure. The source/drain semiconductor layers each have a first thickness over a top side of the semiconductor fin and a second thickness over a lateral side of the semiconductor fin. The first thickness and the second thickness have a difference smaller than about 20 percent of the first thickness.

Abstract: A method includes following steps. A silicon germanium layer is formed on a substrate. A surface layer of the silicon germanium layer is oxidized to form an interfacial layer comprising silicon oxide and germanium oxide. The interfacial layer is nitridated. A metal gate structure is formed over the nitridated interfacial layer.

Abstract: A device includes a semiconductor channel region and a gate structure. The semiconductor channel region is on a substrate. The gate structure is over the semiconductor channel region and comprises a gate dielectric layer, a first gate conductor layer, and a second gate conductor layer. The first gate conductor layer is over the gate dielectric layer. The first gate conductor layer includes oxygen. The second gate conductor layer is over the first gate conductor layer.