Patents by Inventor Zi-Wen Dong
Zi-Wen Dong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8285144Abstract: An optical device for rearranging wavelength channels in an optical network is disclosed. The optical device has a wavelength selective coupler having one input port and a plurality of output ports coupled to a plurality of input ports of an optical grating demultiplexor such as an arrayed waveguide grating. The wavelength channels in each of the input ports are dispersed by the demultiplexor and are directed to a plurality of output ports of the optical grating demultiplexor. As a result, at least one wavelength channel at each of the input ports of the optical grating demultiplexor is coupled into a common output port. The optical device is useful in passive optical networks wherein a same demultiplexor is used for simultaneous multiplexing and demultiplexing of wavelength channels.Type: GrantFiled: July 30, 2010Date of Patent: October 9, 2012Assignee: JDS Uniphase CorporationInventors: Hiroaki Yamada, Barthelemy Fondeur, Jinxi Shen, Zi-Wen Dong, Domenico Di Mola, Jyoti K. Bhardwaj, Yimin Hua
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Publication number: 20110052189Abstract: An optical device for rearranging wavelength channels in an optical network is disclosed. The optical device has a wavelength selective coupler having one input port and a plurality of output ports coupled to a plurality of input ports of an optical grating demultiplexor such as an arrayed waveguide grating. The wavelength channels in each of the input ports are dispersed by the demultiplexor and are directed to a plurality of output ports of the optical grating demultiplexor. As a result, at least one wavelength channel at each of the input ports of the optical grating demultiplexor is coupled into a common output port. The optical device is useful in passive optical networks wherein a same demultiplexor is used for simultaneous multiplexing and demultiplexing of wavelength channels.Type: ApplicationFiled: July 30, 2010Publication date: March 3, 2011Inventors: Hiroaki Yamada, Barthelemy Fondeur, Jinxi Shen, Zi-Wen Dong, Domenico Di Mola, Jyoti K. Bhardwaj, Yimin Hua
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Patent number: 6989962Abstract: The present invention provides a write element for use in magnetic data recording system such as a computer disk drive. The write head utilizes the advantageous properties of high magnetic moments while overcoming the corrosion problems engendered by such materials. The write element includes a magnetic yoke constructed of first and second magnetic poles joined to one another at a back gap. While the majority of the poles are constructed of a high magnetic moment material a layer of relatively low magnetic moment material is provided on the first pole at the back gap portion of the first pole. The relatively low magnetic moment material prevents corrosion of the first pole during subsequent manufacturing of the write head. An electrically conductive coil passes through the magnetic yoke and is insulated there from. By passing an electrical current through the electrical coil, a magnetic flux is generated in the yoke. This magnetic flux then generates a magnetic fringing field in at a write gap of the yoke.Type: GrantFiled: February 24, 2003Date of Patent: January 24, 2006Assignee: Western Digital (Fremont), Inc.Inventors: Zi-Wen Dong, James Wong, Ron Barr
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Patent number: 6947653Abstract: A planar lightwave circuit includes at least one optical waveguide core, and at least one feature proximate the core having a stress-engineered property to balance stress and therefore minimize birefringence affecting the core. A protective passivation layer is formed over the core and the feature to be substantially non-interfering with the balanced stress provided by the feature. The stress balancing feature may be an overcladding layer formed over the core, doped to have a coefficient of thermal expansion approximately matched to that of an underlying substrate, to symmetrically distribute stress in an undercladding between the overcladding and the substrate, away from the core. The protective passivation layer is formed to have a coefficient of thermal expansion approximately matched to that of the overcladding. In one exemplary embodiment, the passivation layer is formed from silicon nitride. Related concepts of stress release grooves, and core overetching, are also disclosed.Type: GrantFiled: October 12, 2001Date of Patent: September 20, 2005Assignee: JDS Uniphase CorporationInventors: Jyoti Kiron Bhardwaj, Robert James Brainard, Zi-Wen Dong, David Dougherty, Erik W. Egan, Niranjan Gopinathan, David K. Nakamoto, Thomas Thuan Nguyen, Sanjay M. Thekdi, Anantharaman Vaidyanathan, Hiroaki Yamada, Yingchao Yan
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Patent number: 6870712Abstract: A disk drive write head (10) having a bottom pole (60), a first insulation layer (64) formed on the bottom pole (60), a coil (38) formed on the first insulation layer (64), a second insulation layer (66) formed on the coil (38), a write gap layer (76) formed on the second insulation layer (66), and a top pole (12) formed on the write gap layer (76), where the top pole (12) is substantially flat. A second embodiment (100) is described which is produced by a damascene process.Type: GrantFiled: June 5, 2001Date of Patent: March 22, 2005Assignee: Western Digital (Fremont), Inc.Inventors: Yingjian Chen, James Wang, Qing He, Zi-Wen Dong, David J. Seagle
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Patent number: 6762910Abstract: The present invention provides a thin film read head having a lower shield pedestal with an adjacent lower extra gap layer. The pedestal may be formed from a lower shield layer with the lower extra gap layer being inset within the lower shield layer so that the top surfaces of the lower extra gap layer and the pedestal are generally planar. This allows for deposition of generally planar lower gap and sensor layers. A sensor element may be defined on the generally planar surface using a bilayer resist structure. The generally planar surface of the sensor layer inhibits resist pooling which could otherwise degrade resist structure and sensor element formation. In a typical embodiment, the read head of the present invention may have a spin valve type sensor element with leads electrically coupled to the sensor element, an upper gap layer extending between the sensor element and the upper shield layer, and an upper extra gap layer disposed between at least a portion of the leads and the upper shield layer.Type: GrantFiled: June 3, 1999Date of Patent: July 13, 2004Assignee: Western Digital (Fremont), Inc.Inventors: Kenneth E. Knapp, Zi-Wen Dong, Ronald A. Barr, Russel Stearns, Bill Crue
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Patent number: 6721138Abstract: An inductive transducer having first and second magnetic pedestals disposed between first and second magnetic pole layers and adjacent to a media-facing surface, the pedestals separated by a submicron, nonmagnetic gap. The first pedestal extends less than the second pedestal from the media-facing surface, defining a short throat height. The second pedestal extends further to provide sufficient area for stitching to the second pole layer. The stitching and the thickness provided by the pedestals allow plural coil layers to be disposed between the pole layers, and the second pedestal, as well as other features, can be defined by high-resolution photolithography. The two coil layers have lower resistance, lower inductance and allow the pole layers to be shorter, improving performance. All or part of either or both of the pedestals may be formed of high magnetic saturation material, further enhancing performance.Type: GrantFiled: October 24, 2001Date of Patent: April 13, 2004Assignee: Western Digital (Fremont), Inc.Inventors: Yingjian Chen, Xizeng Shi, Hugh Craig Hiner, Zi-Wen Dong, Francis Liu, Matthew R. Gibbons, Joyce Anne Thompson, William D. Jensen, Chester Xiaowen Chien, Yugang Wang
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Patent number: 6697553Abstract: A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).Type: GrantFiled: February 15, 2002Date of Patent: February 24, 2004Assignee: JDS Uniphase CorporationInventors: Jyoti Kiron Bhardwaj, Robert James Brainard, David J. Chapman, Douglas E. Crafts, Zi-Wen Dong, David Dougherty, Erik W. Egan, James F. Farrell, Mark B. Farrelly, Niranjan Gopinathan, Kenzo Ishida, David K. Nakamoto, Thomas Thuan Nguyen, Suresh Ramalingam, Steven M. Swain, Sanjay M. Thekdi, Anantharaman Vaidyanathan, Hiroaki Yamada, Yingchao Yan
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Publication number: 20030156789Abstract: A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).Type: ApplicationFiled: February 15, 2002Publication date: August 21, 2003Inventors: Jyoti Kiron Bhardwaj, Robert James Brainard, David J. Chapman, Douglas E. Crafts, Zi-Wen Dong, David Dougherty, Erik W. Egan, James F. Farrell, Mark B. Farrelly, Niranjan Gopinathan, Kenzo Ishida, David K. Nakamoto, Thomas Thuan Nguyen, Suresh Ramalingam, Steven M. Swain, Sanjay M. Thekdi, Anantharaman Vaidyanathan, Hiroaki Yamada, Yingchao Yan
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Publication number: 20030072548Abstract: A planar lightwave circuit includes at least one optical waveguide core, and at least one feature proximate the core having a stress-engineered property to balance stress and therefore minimize birefringence affecting the core. A protective passivation layer is formed over the core and the feature to be substantially non-interfering with the balanced stress provided by the feature. The stress balancing feature may be an overcladding layer formed over the core, doped to have a coefficient of thermal expansion approximately matched to that of an underlying substrate, to symmetrically distribute stress in an undercladding between the overcladding and the substrate, away from the core. The protective passivation layer is formed to have a coefficient of thermal expansion approximately matched to that of the overcladding. In one exemplary embodiment, the passivation layer is formed from silicon nitride. Related concepts of stress release grooves, and core overetching, are also disclosed.Type: ApplicationFiled: October 12, 2001Publication date: April 17, 2003Applicant: Scion Photonics, Inc.Inventors: Jyoti Kiron Bhardwaj, Robert James Brainard, Zi-Wen Dong, David Dougherty, Erik W. Egan, Niranjan Gopinathan, David K. Nakamoto, Thomas Thuan Nguyen, Sanjay M. Thekdi, Anantharaman Vaidyanathan, Hiroaki Yamada, Yingchao Yan
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Patent number: 6515573Abstract: A method and system for providing a magnetoresistive sensor for reading data from a recording media is disclosed. The method and system include providing at least one barrier layer and a free layer having at least one edge. The at least one edge of the free layer is adjacent to the at least one barrier layer. The free layer is ferromagnetic and has a low coercivity. The method and system also include providing at least one hard magnetic layer. The at least one hard magnetic layer has a coercivity greater than the free layer coercivity. The at least one barrier layer is disposed between the at least one hard magnetic layer and the free layer. The at least one barrier layer is sufficiently thin to allow tunneling of charge carriers between the at least one hard magnetic layer and the free layer.Type: GrantFiled: June 19, 2000Date of Patent: February 4, 2003Assignee: Read-Rite CorporationInventors: Zi-Wen Dong, Zhupei Shi, Qunwen Leng
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Patent number: 6496334Abstract: In at least one embodiment, the apparatus of the invention is a read sensor comprising a shield, a sensor element, an extra shield between the shield and the sensor element, an extra gap between the shield and the sensor and adjacent the extra shield, and a gap layer between the sensor element and the extra shield. The sensor element is positioned in a sensor layer. With the extra shield adjacent to the sensor element and separated by only the relatively thin gap layer, high areal recording density and excellent instability of the sensor element is obtained. At the same time, by fabricating the extra shield to be not significantly wider than the sensor element, the potential for shorting is minimized by placing both the gap and the thicker extra gap between the sensor lead elements and the shield.Type: GrantFiled: May 26, 2000Date of Patent: December 17, 2002Assignee: Read-Rite CorportionInventors: Song Pang, Lijun Tong, Zi-Wen Dong, Kevin Lin, Joyce Hsiang
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Publication number: 20020181162Abstract: A disk drive write head (10) having a bottom pole (60), a first insulation layer (64) formed on the bottom pole (60), a coil (38) formed on the first insulation layer (64), a second insulation layer (66) formed on the coil (38), a write gap layer (76) formed on the second insulation layer (66), and a top pole (12) formed on the write gap layer (76), where the top pole (12) is substantially flat.Type: ApplicationFiled: June 5, 2001Publication date: December 5, 2002Inventors: Yingjian Chen, James Wang, Qing He, Zi-Wen Dong, David J. Seagle