Patents by Inventor Zia Abbas

Zia Abbas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230273632
    Abstract: A proportional to-absolute-temperature (PTAT) voltage generating circuit connected between a power supply voltage source and a ground for providing a PTAT voltage at an output terminal of the PTAT voltage generating circuit to act as a temperature sensor is provided. The PTAT voltage generating circuit includes a plurality of PMOS transistors. The plurality of PMOS transistors generates a second PTAT voltage by multiplying a first PTAT voltage by a factor equal to a ratio of a first equivalent resistance (R2) and a second resistance (R1) of a first PMOS transistor (M4). The first equivalent resistance (R2) is obtained from a series combination of the plurality of PMOS transistors. The first PTAT voltage is generated by determining a difference between a base-emitter voltage of a first PNP transistor (T1) and the second PNP transistor (T2).
    Type: Application
    Filed: February 28, 2023
    Publication date: August 31, 2023
    Inventors: Zia Abbas, Abhishek Pullela, Ashfakh Ali, Arpan Jain
  • Publication number: 20230153597
    Abstract: An Integrated Circuit with an automatically re-tuning analog circuit is provided. The Integrated Circuit comprises (a) an analog circuit comprising a plurality of tunable components each configured to respond to a plurality of change control bits, (b) a Process, Voltage Temperature (PVT) characteristics monitor comprising a plurality of PVT sensors, (c) a tuning memory embedded with a machine learning (ML) model of the analog circuit and (d) an artificial intelligence (AI) engine configured to receive a PVT signal input from the plurality of PVT sensors and the machine learning model embedded in the tuning memory. Each tunable component is configured to change its electrical characteristics such that together each of the tunable components is enabled to retune the analog circuit to attain a predefined set of electrical characteristics.
    Type: Application
    Filed: May 27, 2022
    Publication date: May 18, 2023
    Inventors: Koushik De, Khanh Minh Le, Deepthi Amuru, Zia Abbas
  • Patent number: 11416664
    Abstract: The present description relates to a method based on artificial intelligence to implement a wide range of microelectronic circuits that can adapt by themselves to the usage conditions (e.g. loading changes), manufacturing variances or defects (e.g. process variations, device parameter mismatches, device model inaccuracies or changes, etc.), as well as environmental conditions (e.g. voltage, temperature, interference) in order to negate all or part of their effects on the circuit performance characteristics and achieve a very tight set of specifications over the wide range of conditions. Each microelectronic circuit is represented by a neural network model whose behavior is a function of the actual input signals, the usage and environmental conditions.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: August 16, 2022
    Assignee: Analog Intelligent Design, Inc.
    Inventors: Khanh M Le, Koushik De, Deepthi Amuru, Zia Abbas
  • Publication number: 20220092246
    Abstract: A system and method for synthesizing analog design in real-time using an artificial intelligence and machine learning (AI/ML) model are provided. The method includes (i) generating a behavioral model of an analog macro using the AI/ML model; (ii) determining one or more operations that is required to implement the behavioral model by scanning the behavioral model; (iii) selecting, using the AI/ML model, the analog macro based on at least one specification that corresponds to the analog macro; (iv) synthesizing, the analog macro that is selected by the AI/ML model 214 and one or more leaf cells for each selected analog macro of the behavioral architectural implementation to obtain a gate-level circuit design based on a figure of merit (FoM) of the analog macro and (v) determining, using the AI/ML model, the analog circuit design for the integrated circuit system based on the gate level circuit design that is synthesized.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 24, 2022
    Inventors: Zia Abbas, Koushik De
  • Publication number: 20210182466
    Abstract: The present description relates to a method based on artificial intelligence to implement a wide range of microelectronic circuits that can adapt by themselves to the usage conditions (e.g. loading changes), manufacturing variances or defects (e.g. process variations, device parameter mismatches, device model inaccuracies or changes, etc.), as well as environmental conditions (e.g. voltage, temperature, interference) in order to negate all or part of their effects on the circuit performance characteristics and achieve a very tight set of specifications over the wide range of conditions. Each microelectronic circuit is represented by a neural network model whose behavior is a function of the actual input signals, the usage and environmental conditions.
    Type: Application
    Filed: November 3, 2020
    Publication date: June 17, 2021
    Inventors: Khanh M Le, Koushik De, Deepthi Amuru, Zia Abbas