Patents by Inventor Ziaul Karim
Ziaul Karim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11444053Abstract: The present disclosure is directed to a compact vertical oven for reflow of solder bumps for backend processes in semiconductor wafer assembly and packaging. This disclosure describes a vertical oven which uses a plurality of wafers (e.g., an example value is 50-100 wafers) in a batch with controlled injection of the reducing agent (e.g. formic acid), resulting in a process largely free of contamination. This disclosure describes controlled formic acid flow through a vertical system using laminar flow technology in a sub-atmospheric pressure environment, which is not currently available in the industry. The efficacy of the process depends on effective formic acid vapor delivery, integrated temperature control during heating and cooling, and careful design of the vapor flow path with exhaust. Zone-dependent reaction dynamics managed by vapor delivery process, two-steps temperature ramp control, and controlled cooling process and formic acid content ensures the effective reaction without any flux.Type: GrantFiled: April 17, 2020Date of Patent: September 13, 2022Assignee: YIELD ENGINEERING SYSTEMS, INC.Inventors: M Ziaul Karim, Randy Hall, Peter Krotov
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Patent number: 11401607Abstract: A method for ALD coating of a substrate with a layer containing Ti, Si, N, wherein a reaction gas and then a flushing gas are introduced into a process chamber holding the substrate in a plurality of successive steps, each in one or more cycles, wherein TiN is deposited in a first step with a reaction gas containing Ti and a reaction gas containing N, TiSi is deposited in a second step with a reaction gas containing Ti and a reaction gas containing Si, and in a third step following the second step, TiSiN is deposited with a reaction gas containing Ti, with a reaction gas containing N and with a reaction gas containing Si.Type: GrantFiled: June 2, 2017Date of Patent: August 2, 2022Assignee: Eugenus, Inc.Inventors: Vinayak Veer Vats, M. Ziaul Karim, Bo Seon Choi
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Patent number: 11335662Abstract: A solder reflow oven may include a reflow chamber and a plurality of vertically spaced apart wafer-support plates positioned in the reflow chamber. A plurality of semiconductor wafers each including a solder are configured to be disposed in the reflow chamber such that each semiconductor wafer is disposed proximate to, and vertically spaced apart from, a wafer-support plate. Each wafer-support plate may include at least one of liquid-flow channels or resistive heating elements. A control system control the flow of a hot liquid through the channels or activate the heating elements to heat a wafer to a temperature above the solder reflow temperature.Type: GrantFiled: September 2, 2021Date of Patent: May 17, 2022Assignee: YIELD ENGINEERING SYSTEMS, INC.Inventors: M Ziaul Karim, Randy Hall, Peter Krotov
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Publication number: 20210398937Abstract: A solder reflow oven may include a reflow chamber and a plurality of vertically spaced apart wafer-support plates positioned in the reflow chamber. A plurality of semiconductor wafers each including a solder are configured to be disposed in the reflow chamber such that each semiconductor wafer is disposed proximate to, and vertically spaced apart from, a wafer-support plate. Each wafer-support plate may include at least one of liquid-flow channels or resistive heating elements. A control system control the flow of a hot liquid through the channels or activate the heating elements to heat a wafer to a temperature above the solder reflow temperature.Type: ApplicationFiled: September 2, 2021Publication date: December 23, 2021Applicant: Yield Engineering Systems, Inc.Inventors: M Ziaul Karim, Randy Hall, Peter Krotov
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Publication number: 20210265301Abstract: The present disclosure is directed to a compact vertical oven for reflow of solder bumps for backend processes in semiconductor wafer assembly and packaging. This disclosure describes a vertical oven which uses a plurality of wafers (e.g., an example value is 50-100 wafers) in a batch with controlled injection of the reducing agent (e.g. formic acid), resulting in a process largely free of contamination. This disclosure describes controlled formic acid flow through a vertical system using laminar flow technology in a sub-atmospheric pressure environment, which is not currently available in the industry. The efficacy of the process depends on effective formic acid vapor delivery, integrated temperature control during heating and cooling, and careful design of the vapor flow path with exhaust. Zone-dependent reaction dynamics managed by vapor delivery process, two-steps temperature ramp control, and controlled cooling process and formic acid content ensures the effective reaction without any flux.Type: ApplicationFiled: April 17, 2020Publication date: August 26, 2021Inventors: M Ziaul Karim, Randy Hall, Peter Krotov
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Patent number: 10544519Abstract: During a pre-treat process, hydrogen plasma is used to remove contaminants (e.g., oxygen, carbon) from a surface of a wafer. The hydrogen plasma may be injected into the plasma chamber via an elongated injector nozzle. Using such elongated injector nozzle, a flow of hydrogen plasma with a significant radial velocity flows over the wafer surface, and transports volatile compounds and other contaminant away from the wafer surface to an exhaust manifold. A protective liner made from crystalline silicon or polysilicon may be disposed on an inner surface of the plasma chamber to prevent contaminants from being released from the surface of the plasma chamber. To further decrease the sources of contaminants, an exhaust restrictor made from silicon may be employed to prevent hydrogen plasma from flowing into the exhaust manifold and prevent volatile compounds and other contaminants from flowing from the exhaust manifold back into the plasma chamber.Type: GrantFiled: August 25, 2017Date of Patent: January 28, 2020Assignee: AIXTRON SEInventors: Stephen Edward Savas, Miguel Angel Saldana, Dan Lester Cossentine, Hae Young Kim, Subramanian Tamilmani, Niloy Mukherjee, M Ziaul Karim
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Publication number: 20190062947Abstract: During a pre-treat process, hydrogen plasma is used to remove contaminants (e.g., oxygen, carbon) from a surface of a wafer. The hydrogen plasma may be injected into the plasma chamber via an elongated injector nozzle. Using such elongated injector nozzle, a flow of hydrogen plasma with a significant radial velocity flows over the wafer surface, and transports volatile compounds and other contaminant away from the wafer surface to an exhaust manifold. A protective liner made from crystalline silicon or polysilicon may be disposed on an inner surface of the plasma chamber to prevent contaminants from being released from the surface of the plasma chamber. To further decrease the sources of contaminants, an exhaust restrictor made from silicon may be employed to prevent hydrogen plasma from flowing into the exhaust manifold and prevent volatile compounds and other contaminants from flowing from the exhaust manifold back into the plasma chamber.Type: ApplicationFiled: August 25, 2017Publication date: February 28, 2019Inventors: Stephen Edward Savas, Miquel Angel Saldana, Dan Lester Cossentine, Hae Young Kim, Subramanian Tamilmani, Niloy Mukherjee, M. Ziaul Karim
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Publication number: 20180350657Abstract: The disclosed technology generally relates to semiconductor structures and their fabrication, and more particularly to diffusion barrier structures containing Ti, Si, N and methods of forming same. A method of forming an electrically conductive diffusion barrier comprises providing a substrate in a reaction chamber and forming a titanium silicide (TiSi) region on the substrate by alternatingly exposing the substrate to a titanium-containing precursor and a first silicon-containing precursor. The method additionally comprises forming a titanium silicon nitride (TiSiN) region on the TiSi region by alternatingly exposing the substrate to a titanium-containing precursor, a nitrogen-containing precursor and a second silicon-containing precursor. The method can optionally include, prior to forming the TiSi region, forming a titanium nitride (TiN) region by alternatingly exposing the substrate to a titanium-containing precursor and a nitrogen-containing precursor.Type: ApplicationFiled: May 31, 2018Publication date: December 6, 2018Inventors: Vinayak Veer Vats, M. Ziaul Karim, Bo Seon Choi, Somilkumar J. Rathi, Niloy Mukherjee
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Publication number: 20180347040Abstract: A method for ALD coating of a substrate with a layer containing Ti, Si, N, wherein a reaction gas and then a flushing gas are introduced into a process chamber holding the substrate in a plurality of successive steps, each in one or more cycles, wherein TiN is deposited in a first step with a reaction gas containing Ti and a reaction gas containing N, TiSi is deposited in a second step with a reaction gas containing Ti and a reaction gas containing Si, and in a third step following the second step, TiSiN is deposited with a reaction gas containing Ti, with a reaction gas containing N and with a reaction gas containing Si.Type: ApplicationFiled: June 2, 2017Publication date: December 6, 2018Inventors: Vinayak Veer VATS, M. Ziaul KARIM, Bo Seon CHOI
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Publication number: 20110253046Abstract: A gas distribution system for a reactor having at least two distinct gas source orifice arrays displaced from one another along an axis defined by a gas flow direction from the gas source orifice arrays towards a work-piece deposition surface such that at least a lower one of the gas source orifice arrays is located between a higher one of the gas source orifice arrays and the work-piece deposition surface. Orifices in the higher one of the gas source orifice arrays may spaced an average of 0.2-0.8 times a distance between the higher one of the gas source orifice arrays and the work-piece deposition surface, while orifices in the lower one of the gas source orifice arrays may be spaced an average of 0.1-0.4 times a distance between the higher one of the gas source orifice array and the work-piece deposition surface.Type: ApplicationFiled: June 24, 2011Publication date: October 20, 2011Inventors: Jeremie J. Dalton, M. Ziaul Karim, Ana R. Londergan
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Patent number: 7981472Abstract: A method of introducing gasses through a gas distribution system into a reactor involves flowing the gasses through at least two distinct gas source orifice arrays displaced from one another along an axis defined by a gas flow direction from the gas source orifice arrays towards a work-piece. During different time intervals, a purge gas and different reactive precursors are flowed into the reactor from different ones of the gas source orifice arrays. One of the precursors may be associated with a soft saturating atomic layer deposition half reaction and another of the precursors associated with a strongly saturating atomic layer deposition half reaction. An upper one of the gas source orifice arrays may be a relatively planar gas orifice array.Type: GrantFiled: September 3, 2009Date of Patent: July 19, 2011Assignee: Aixtron, Inc.Inventors: Jeremie J. Dalton, M. Ziaul Karim, Ana R. Londergan
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Publication number: 20090324829Abstract: A gas distribution system for a reactor having at least two distinct gas source orifice arrays displaced from one another along an axis defined by a gas flow direction from the gas source orifice arrays towards a work-piece deposition surface such that at least a lower one of the gas source orifice arrays is located between a higher one of the gas source orifice arrays and the work-piece deposition surface. Orifices in the higher one of the gas source orifice arrays may spaced an average of 0.2-0.8 times a distance between the higher one of the gas source orifice arrays and the work-piece deposition surface, while orifices in the lower one of the gas source orifice arrays may be spaced an average of 0.1-0.4 times a distance between the higher one of the gas source orifice arrays and the work-piece deposition surface.Type: ApplicationFiled: September 3, 2009Publication date: December 31, 2009Inventors: Jeremie J. Dalton, M. Ziaul Karim, Ana R. Londergan
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Patent number: 7595088Abstract: A method of depositing a silicon oxide layer over a substrate having a trench formed between adjacent raised surfaces. In one embodiment the silicon oxide layer is formed in a multistep process that includes depositing a first portion of layer over the substrate and within the trench by forming a high density plasma process that has simultaneous deposition and sputtering components from a first process gas comprising a silicon source, an oxygen source and helium and/or molecular hydrogen with highD/S ratio, for example, 10-20 and, thereafter, depositing a second portion of the silicon oxide layer over the substrate and within the trench by forming a high density plasma process that has simultaneous deposition and sputtering components from a second process gas comprising a silicon source, an oxygen source and molecular hydrogen with a lowerD/S ratio of, for example, 3-10.Type: GrantFiled: August 10, 2004Date of Patent: September 29, 2009Assignee: Applied Materials, Inc.Inventors: Bikram Kapoor, M. Ziaul Karim, Anchuan Wang
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Patent number: 7294588Abstract: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.Type: GrantFiled: March 24, 2006Date of Patent: November 13, 2007Assignee: Applied Materials, Inc.Inventors: M. Ziaul Karim, DongQing Li, Jeong Soo Byun, Thanh N. Pham
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Patent number: 7205240Abstract: A gapfill process is provided using cycling of HDP-CVD deposition, etching, and deposition step. The fluent gas during the first deposition step includes an inert gas such as He, but includes H2 during the remainder deposition step. The higher average molecular weight of the fluent gas during the first deposition step provides some cusping over structures that define the gap to protect them during the etching step. The lower average molecular weight of the fluent gas during the remainder deposition step has reduced sputtering characteristics and is effective at filling the remainder of the gap.Type: GrantFiled: June 4, 2003Date of Patent: April 17, 2007Assignee: Applied Materials, Inc.Inventors: M. Ziaul Karim, Bikram Kapoor, Anchuan Wang, Dong Qing Li, Katsunari Ozeki, Manoj Vellaikal, Zhuang Li
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Applications and methods of making nitrogen-free anti-reflective layers for semiconductor processing
Patent number: 7052988Abstract: A nitrogen-free anti-reflective layer for use in semiconductor photolithography is fabricated in a chemical vapor deposition process, optionally plasma-enhanced, using a gaseous mixture of carbon, silicon, and oxygen sources. By varying the process parameters, acceptable values of the refractive index n and extinction coefficient k can be obtained. The nitrogen-free anti-reflective layer produced by this technique eliminates the mushrooming and footing problems found with conventional anti-reflective layers.Type: GrantFiled: February 5, 2004Date of Patent: May 30, 2006Assignee: Novellus Systems, Inc.Inventors: Bart van Schravendijk, Ming Li, Jason Tian, Tom Mountsier, M. Ziaul Karim -
Patent number: 7049211Abstract: A process is provided for depositing an undoped silicon oxide film on a substrate disposed in a process chamber. A process gas that includes SiF4, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The undoped silicon oxide film is deposited over the substrate with the plasma using a process that has simultaneous deposition and sputtering components.Type: GrantFiled: March 25, 2005Date of Patent: May 23, 2006Assignee: Applied MaterialsInventors: M. Ziaul Karim, DongQing Li, Jeong Soo Byun, Thanh N. Pham
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Patent number: 7033945Abstract: A method of filling a gap formed between adjacent raised surfaces on a substrate. In one embodiment the method comprises depositing a boron-doped silica glass (BSG) layer over the substrate to partially fill the gap using a thermal CVD process; exposing the BSG layer to a steam ambient at a temperature above the BSG layer's Eutectic temperature; removing an upper portion of the BSG layer by exposing the layer to a fluorine-containing etchant; and depositing an undoped silica glass (USG) layer over the BSG layer to fill the remainder of the gap.Type: GrantFiled: June 1, 2004Date of Patent: April 25, 2006Assignee: Applied MaterialsInventors: Jeong Soo Byun, Zheng Yuan, Shankar Venkataraman, M. Ziaul Karim, Thanh N. Pham, Ellie Y. Yieh
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Patent number: 6958112Abstract: Methods and systems are provided for depositing silicon oxide in a gap on a substrate. The silicon oxide is formed by flowing a process gas into a process chamber and forming a plasma having an overall ion density of at least 1011 ions/cm3. The process gas includes H2, a silicon source, and an oxidizing gas reactant, and deposition into the gap is achieved using a process that has simultaneous deposition and sputtering components. The probability of forming a void is reduced by ensuring that the plasma has a greater density of ions having a single oxygen atom than a density of ions having more than one oxygen atom.Type: GrantFiled: May 27, 2003Date of Patent: October 25, 2005Assignee: Applied Materials, Inc.Inventors: M. Ziaul Karim, Farhad K. Moghadam, Siamak Salimian
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Patent number: 6903031Abstract: A process is provided for depositing an undoped silicon oxide film on a substrate disposed in a process chamber. A process gas that includes SiF4, H2, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The undoped silicon oxide film is deposited over the substrate with the plasma using a process that has simultaneous deposition and sputtering components. A temperature of the substrate during such depositing is greater than 450° C.Type: GrantFiled: September 3, 2003Date of Patent: June 7, 2005Assignee: Applied Materials, Inc.Inventors: M. Ziaul Karim, DongQing Li, Jeong Soo Byun, Thanh N. Pham