Abstract: A fully differential level conversion circuit includes a positive signal branch, a negative signal branch and a coupling branch. The negative signal branch has identical structural features with the positive signal branch, which includes a drive terminal and a load terminal, an external fully differential signal is inputted to the drive terminals of the positive signal branch and the negative signal branch correspondingly. The coupling branch includes a first group of active couplers which forms a dual structure with the drive terminal of the positive signal branch and a second group of active couplers which form another dual structure with the drive terminal of the negative signal branch, both of which are connected between the drive terminals and load terminals. The fully differential level conversion circuit realizes applications in the signal processing process which has low power consumption and high-speed, and improves duty cycle of the output signal.

Abstract: A high-frequency bandwidth amplifying circuit includes a forward channel and a backward channel. An input terminal of the forward channel and an external forward input terminal are connected; an output terminal of the forward channel and a forward output port are connected. An input terminal of the backward channel and an external backward input terminal are connected; an output terminal of the backward channel and a backward output port are connected. The high-frequency bandwidth amplifying circuit further includes a feedback network. The forward channel includes a first operational amplifier and a second operational amplifier. An input terminal of the first operational amplifier is connected to the external forward input terminal; an output terminal of the first operational amplifier is connected to an input terminal of the second operational amplifier; and an output terminal of the second operational amplifier is connected to the forward output port.

Abstract: A signal amplitude detection circuit includes a detector and a trimming algorithm module, and the detector having a preset baseline threshold reference value and an output terminal connected with the trimming algorithm module which is arranged for recording and decoding an output result of the detector to output an amplitude code value, and generating a control signal for controlling the baseline threshold reference value rise to a power supply level from a ground level or drop to the ground level from the power supply level, and the output result of the detector being “1” if a crossover occurs between the baseline threshold reference value and the detected signal; otherwise being “0”. The signal amplitude detection circuit detects the signal amplitude in a digital way, which has simpler structure, lower power consumption, reduced size of chips, and stable and accurate detection result without PVT drift.

Abstract: A high-frequency bandwidth amplifier circuit comprises: a push-pull amplifier, a feedback resistor, a first active inductor, and a second active inductor. An input terminal of the push-pull amplifier is connected with an external input terminal. An output terminal of the push-pull amplifier is connected with an output port. A first end of the feedback resistor is connected with the external input terminal. A second end of the feedback resistor is connected with the output port. A first end of the first active inductor is connected with an external power source. A second end of the first active inductor is connected with the output port. A first end of the second active inductor is grounded. A second end of the second active inductor is connected with the output port.

Abstract: A locking detection circuit for CDR circuits includes a first frequency divider, a second frequency divider, a first sampler, a second sampler, and a locking detector, with a data signal outputted by a CDR circuit being inputted to the first frequency divider and the first sampler respectively, the first frequency divider being connected with the first sampler, a clock pulse outputted by the CDR circuit being inputted to the second frequency divider and the second sampler respectively, output terminals of the first and second samplers being connected with the locking detector which is for detecting if rising edges of the data signal outputted and the clock pulse outputted are aligned, and then outputting a detection result. The circuit size and power consumption is reduced, and it is applicable to spread spectrum carrier with high data rate over 1 Gbps and with any protocol, whose application scope is broadened.

Abstract: A fully differential level conversion circuit includes a positive signal branch, a negative signal branch and a coupling branch. The negative signal branch has identical structural features with the positive signal branch, which includes a drive terminal and a load terminal, an external fully differential signal is inputted to the drive terminals of the positive signal branch and the negative signal branch correspondingly. The coupling branch includes a first group of active couplers which forms a dual structure with the drive terminal of the positive signal branch and a second group of active couplers which form another dual structure with the drive terminal of the negative signal branch, both of which are connected between the drive terminals and load terminals. The fully differential level conversion circuit realizes applications in the signal processing process which has low power consumption and high-speed, and improves duty cycle of the output signal.

Abstract: A locking detection circuit for CDR circuits includes a first frequency divider, a second frequency divider, a first sampler, a second sampler, and a locking detector, with a data signal outputted by a CDR circuit being inputted to the first frequency divider and the first sampler respectively, the first frequency divider being connected with the first sampler, a clock pulse outputted by the CDR circuit being inputted to the second frequency divider and the second sampler respectively, output terminals of the first and second samplers being connected with the locking detector which is for detecting if rising edges of the data signal outputted and the clock pulse outputted are aligned, and then outputting a detection result. The circuit size and power consumption is reduced, and it is applicable to spread spectrum carrier with high data rate over 1 Gbps and with any protocol, whose application scope is broadened.

Abstract: A frequency locking system for locking a clock frequency in a CDR circuit without crystal oscillator is provided. Reference data information is inputted into a first low-pass filter; the first low-pass filter is connected to a first swing detector; the first swing detector is connected to a non-inverting terminal of a comparator; an output terminal of the comparator is connected to a charge pump; the charge pump is connected to a first terminal of a capacitor; the capacitor is grounded. The capacitor is also connected to a voltage-controlled oscillator; the voltage-controlled oscillator is connected to a code pattern conversion generator; the code pattern conversion generator is connected to of a second low-pass filter; the second low-pass filter is connected to an input terminal of a second swing detector; an output terminal of the second swing detector is connected to an inverting terminal of the comparator.

Abstract: A signal amplitude detection circuit includes a detector and a trimming algorithm module, and the detector having a preset baseline threshold reference value and an output terminal connected with the trimming algorithm module which is arranged for recording and decoding an output result of the detector to output an amplitude code value, and generating a control signal for controlling the baseline threshold reference value rise to a power supply level from a ground level or drop to the ground level from the power supply level, and the output result of the detector being “1” if a crossover occurs between the baseline threshold reference value and the detected signal; otherwise being “0”. The signal amplitude detection circuit detects the signal amplitude in a digital way, which has simpler structure, lower power consumption, reduced size of chips, and stable and accurate detection result without PVT drift.

Abstract: A frequency locking system for locking a clock frequency in a CDR circuit without crystal oscillator is provided. Reference data information is inputted into a first low-pass filter; the first low-pass filter is connected to a first swing detector; the first swing detector is connected to a non-inverting terminal of a comparator; an output terminal of the comparator is connected to a charge pump; the charge pump is connected to a first terminal of a capacitor; the capacitor is grounded. The capacitor is also connected to a voltage-controlled oscillator; the voltage-controlled oscillator is connected to a code pattern conversion generator; the code pattern conversion generator is connected to of a second low-pass filter; the second low-pass filter is connected to an input terminal of a second swing detector; an output terminal of the second swing detector is connected to an inverting terminal of the comparator.

Abstract: A high-frequency bandwidth amplifying circuit includes a forward channel and a backward channel. An input terminal of the forward channel and an external forward input terminal are connected; an output terminal of the forward channel and a forward output port are connected. An input terminal of the backward channel and an external backward input terminal are connected; an output terminal of the backward channel and a backward output port are connected. The high-frequency bandwidth amplifying circuit further includes a feedback network. The forward channel includes a first operational amplifier and a second operational amplifier. An input terminal of the first operational amplifier is connected to the external forward input terminal; an output terminal of the first operational amplifier is connected to an input terminal of the second operational amplifier; and an output terminal of the second operational amplifier is connected to the forward output port.

Abstract: A high-frequency bandwidth amplifier circuit comprises: a push-pull amplifier, a feedback resistor, a first active inductor, and a second active inductor. An input terminal of the push-pull amplifier is connected with an external input terminal. An output terminal of the push-pull amplifier is connected with an output port. A first end of the feedback resistor is connected with the external input terminal A second end of the feedback resistor is connected with the output port. A first end of the first active inductor is connected with an external power source. A second end of the first active inductor is connected with the output port. A first end of the second active inductor is grounded. A second end of the second active inductor is connected with the output port.

Abstract: An interpolation circuit, includes a bias generating module, a load module consisting of a current source sub-module and a load resistance sub-module, first and second clock control modules, and an output module. The first clock control module includes a first input sub-module, a first source terminal negative feedback sub-module, a first multiplex switch sub-module and a first multiplex current sink sub-module. The bias generating module includes first, second and third FETs, and a bias current terminal. The current source sub-module includes fourth and fifth FETs. The load resistance sub-module includes first and second resistors. The first input sub-module includes sixth and seventh FETs. The first source terminal negative feedback sub-module includes a third resistor and a first capacitor. The first multiplex switch sub-module includes first and second groups of switches. The first multiplex current sink sub-module includes first and second groups of FETs. An interpolation system is further provided.

Abstract: An interpolation circuit, includes a bias generating module, a load module consisting of a current source sub-module and a load resistance sub-module, first and second clock control modules, and an output module. The first clock control module includes a first input sub-module, a first source terminal negative feedback sub-module, a first multiplex switch sub-module and a first multiplex current sink sub-module. The bias generating module includes first, second and third FETs, and a bias current terminal. The current source sub-module includes fourth and fifth FETs. The load resistance sub-module includes first and second resistors. The first input sub-module includes sixth and seventh FETs. The first source terminal negative feedback sub-module includes a third resistor and a first capacitor. The first multiplex switch sub-module includes first and second groups of switches. The first multiplex current sink sub-module includes first and second groups of FETs. An interpolation system is further provided.

Abstract: A spread spectrum clock signal detection system includes: a spread spectrum clock signal input terminal; a reference clock signal input terminal; a frequency difference detection module connected with the spread spectrum clock signal input terminal and the reference clock signal input terminal; a spread spectrum pulse detection module connected with the spread spectrum clock signal input terminal, the reference clock signal input terminal and the frequency difference detection module; a spread spectrum value calculating module connected with the spread spectrum pulse detection module; a spread spectrum value reference input terminal connected with the spread spectrum value calculating module; and an output module connected with the spread spectrum value calculating module, wherein the spread spectrum clock signal detection system judges whether the spread spectrum clock signal exists according to the information of the spread spectrum value with magnitude and direction.

Abstract: An adaptive equalization system includes an equalizer, a common-mode extraction buffer unit, a low-pass filter unit, a first and second energy compare units, a current comparator, and a digital control unit. The common-mode extraction buffer unit transmits a full spectral energy of an input signal received by the equalizer to the first energy compare unit and the low-pass filter unit, and extracts a common-mode signal of the input signal to the second energy compare unit. The first and second energy compare units respectively output a current signal characterized by the high-frequency energy and a current signal characterized by the low-frequency energy to the current comparator. Based on the compare result outputted by the current comparator, the digital control unit outputs an equalization control signal to the equalizer. The adaptive equalization system has the simple structure, and reduces the power consumption, the area and the manufacturing cost of the chip.

Abstract: A spread spectrum generating circuit comprises an external PLL and an internal PLL. The external PLL comprises a phase detector, a low-pass filter, a voltage-controlled oscillator and a frequency divider, each of them connecting successively. The frequency divider is connected to the phase detector in order to form an external loop. The internal PLL comprises the phase detector, the low-pass filter and the voltage-controlled oscillator of the external PLL, each of them connecting successively. An output terminal of the voltage-controlled oscillator connects with a counter, and the output terminal of the counter connects to an input of the oscillator in order to form an internal loop. The present invention is compatible with the conventional ones, and has lower design risk and higher circuit reliability; compared with the general circuit, it has drastically reduced the area and power consumption, which allows more flexible design and meets more demands.

Abstract: A front-end equalizer and amplifier circuit includes two pairs of fully differential pair transistors, wherein the tail currents of one pair of transistors are connected with ground and connected with each other through the capacitive component to realize the connection between the pair of transistors and the feedback capacitor, the tail currents of the other pair of transistors are connected with ground and connected with each other through the resistive component to realize the connection between the other pair of transistors and the feedback resistor, the output positive and negative ends of each pair of transistors are connected with each other through the inductive component, thus forming the load for connecting the voltage source. The circuit increases the high frequency gain. Its single-stage gain is equivalent to the multi-stage gain. Compared with the traditional multi-stage structure, the present invention decreases the power consumption and area, and improves the reliability.

Abstract: An adaptive equalization system includes an equalizer, a common-mode extraction buffer unit, a low-pass filter unit, a first and second energy compare units, a current comparator, and a digital control unit. The common-mode extraction buffer unit transmits a full spectral energy of an input signal received by the equalizer to the first energy compare unit and the low-pass filter unit, and extracts a common-mode signal of the input signal to the second energy compare unit. The first and second energy compare units respectively output a current signal characterized by the high-frequency energy and a current signal characterized by the low-frequency energy to the current comparator. Based on the compare result outputted by the current comparator, the digital control unit outputs an equalization control signal to the equalizer. The adaptive equalization system has the simple structure, and reduces the power consumption, the area and the manufacturing cost of the chip.

Abstract: A phase delay line comprises a phase-locked loop, a duty-cycle adjusting ring and a voltage-sharing to time-sharing converter, wherein the phase-locked loop and the duty-cycle adjusting ring form a loop, and one output of the phase-locked loop is connected with the input of the voltage-sharing to time-sharing converter. The voltage can be precisely divided, and the number of the phases can be easily controlled and expanded. The band gap reference technology enables the working points not affected by the temperature. The negative feedback mechanism of the phase-locked loop determines the period, phase, duty-cycle of the sawtooth wave are same with the reference clock. The ascending and descending time of the sawtooth wave are precisely equal.