Abstract: Methods for fabricating memory devices including capacitors are disclosed. In one aspect, a method of fabricating a memory device including capacitors is described, where each capacitor includes a first electrode and a second electrode separated by an isolation layer. The method includes providing a first wafer including a sacrificial material and the first electrodes disposed in first holes and in contact with the sacrificial material, hybrid bonding the first wafer with a second wafer including a complementary metal-oxide-semiconductor (CMOS) device, removing the sacrificial material to expose the first electrodes, depositing the isolation layer on the first electrodes, and forming the second electrodes on the isolation layer.

Abstract: A semiconductor device and methods for forming the same are provided. The method includes: forming a plurality of first trenches having a first width during forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction; forming a spacer in each groove, where the spacer is laterally extending along the first lateral direction; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction.

Abstract: In certain aspects, a semiconductor device includes a vertical transistor, a metal bit line, and a pad layer. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The metal bit line extends in a second direction perpendicular to the first direction and coupled to a terminal of the vertical transistor via an ohmic contact. The pad layer is positioned between the gate electrode and the metal bit line in the first direction. The gate dielectric and the pad layer have different dielectric materials.

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a word line extending along a first direction. The semiconductor device may include a bit line extending along a second direction. The second direction may intersect with the first direction. The semiconductor device may include a first conductive connection structure located between a first surface and the word line. An end of the first conductive connection structure may be connected to the word line, and the first surface and a second surface may be two surfaces of the semiconductor device opposite to each other along the first direction. The semiconductor device may include a second conductive connection structure located between the second surface and the bit line. An end of the second conductive connection structure may be connected to the bit line.

Abstract: Described is interaction image processing, including receiving a stroke added by a user to a displayed first image by using an operable control, where the stroke is used to represent a local area that needs to be changed in the displayed first image. A prompt corresponding to the stroke is displayed, where the prompt represents a modification target of the local area. A second image is generated based on the prompt, the stroke, and the displayed first image. The second image is displayed, where the second image presents the modification target in the local area and is identical to or similar to the displayed first image in a remaining area.

Abstract: Systems, devices, and methods for managing word lines in semiconductor devices are provided. In one aspect, a semiconductor device includes multiple blocks. Each block includes multiple rows of memory cells. Each row of memory cells extends along a first direction. A memory cell includes a transistor having a gate extending along a second direction perpendicular to the first direction. The semiconductor device also includes multiple word lines. A word line is coupled to gates of transistors of two adjacent rows of memory cells of two adjacent blocks that are spaced by a corresponding isolating region. The word line extends along the first direction. The semiconductor device further includes multiple conductive structures, and multiple insulating regions configured to separate adjacent word lines. The word line is connected to a corresponding conductive. An area of the corresponding conductive structure is within an area of the corresponding isolating region between two adjacent blocks.

Abstract: According to one aspect of the present disclosure, a memory is provided. The memory may include a plurality of blocks each including a first semiconductor structure. The first semiconductor structure includes a memory cell array. The memory cell array may include a plurality of storage capacitors. The storage capacitor may include a first plate, a second plate, and a dielectric layer located between the first plate and the second plate. The second plates of the plurality of storage capacitors in the block may be connected, and the second plates of the storage capacitors of at least two blocks of the plurality of blocks may be connected.

Abstract: Systems, devices, methods for managing peripheral circuitries in semiconductor devices are provided. In one aspect, a semiconductor device includes a first semiconductor structure that includes a memory array and a first circuitry coupled to the memory array and a second semiconductor structure that includes a second circuitry. The first semiconductor structure includes a first bonding layer, and the second semiconductor structure includes a second bonding layer. The first bonding layer and the second bonding layer are in contact with each other. The first circuitry and the second circuitry are coupled together.

Abstract: Systems, devices, and formation methods for a semiconductor device are provided. In one aspect, a semiconductor device includes semiconductor structures and at least one control structure. Each of the semiconductor structures includes a memory array and a first circuitry coupled to the memory array. The control structure includes second circuitries for the semiconductor structures. Each of the second circuitries is coupled to a memory array of a respective semiconductor structure of the semiconductor structures. The semiconductor structures and the at least one control structure are stacked together along a direction.

Abstract: Systems, devices, and methods for managing three-dimensional (3D) semiconductor devices are provided. In one aspect, a semiconductor device includes an array structure having a plurality of memory cells. A memory cell of the plurality of memory cells includes a transistor and a capacitor that are stacked together. The transistor includes a transistor body, a first terminal, a second terminal, and a gate structure. The first terminal of the transistor is in contact with a first electrode of the capacitor along the first direction. The gate structure includes a conductive film having an angled or curved end closer to the first terminal of the transistor than the second terminal of the transistor.

Abstract: The present disclosure describes memory systems and devices having vertical transistors in one-time-program (OTP) memory cells and fabrication methods thereof. An example semiconductor device includes a first array of memory cells including at least a first memory cell. The first memory cell includes a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction. The first array of memory cells is in a first area of a first semiconductor structure of the semiconductor device. The semiconductor device further includes a second array of memory cells including at least a second memory cell. The second memory cell includes a second vertical transistor in a second area of the first semiconductor structure. The second area is adjacent to the first area in a second direction perpendicular to the first direction.

Abstract: The present disclosure discloses a semiconductor device and a fabrication method thereof. The semiconductor device includes a plurality of first gate structures and second gate structures extending in a first direction and arranged alternatively in a second direction. The first gate structure includes a first isolation structure. The second gate structure includes a second isolation structure. The first isolation structure and the second isolation structure adjacent to each other in the second direction are disposed oppositely, and the first isolation structure and the second isolation structure are both located on one end in the first direction. The present disclosure may improve the yield and the reliability.

Abstract: Methods for fabricating memory devices including capacitors are disclosed. In one aspect, a method of fabricating a memory device including capacitors is described, where each capacitor includes a first electrode and a second electrode separated by an isolation layer. The method includes providing a first wafer including a sacrificial material and the first electrodes disposed in first holes and in contact with the sacrificial material, hybrid bonding the first wafer with a second wafer including a complementary metal-oxide-semiconductor (CMOS) device, removing the sacrificial material to expose the first electrodes, depositing the isolation layer on the first electrodes, and forming the second electrodes on the isolation layer.

Abstract: A semiconductor structure and a fabrication method thereof, a memory and a memory system are provided. The method includes: forming a plurality of capacitor holes penetrating through a first stack layer comprising a first region and a second region where the capacitor holes are located; forming a first electrode layer on inner walls of the capacitor holes; forming a dielectric layer in the first region and the second region; forming a second electrode layer on a side of the dielectric layer; removing the second electrode layer on the first stack layer in the second region; and forming a contact structure penetrating through the first stack layer in the second region. The method can prevent an etch loading effect from occurring in the first region during formation of the capacitor holes, which is favorable to form capacitor structures with a uniform size, thus improving reliability of the capacitor structures.

Abstract: A semiconductor structure, a fabrication method thereof, a memory, and a memory system are provided. The method may include forming a plurality of capacitor holes extending through a stack of layers in the first region and the second region of the stack of layers. The method may include forming a first electrode layer over the inside walls of the respective capacitor holes. The method may include forming a dielectric layer over the stack of layers. The method may include removing at least part of the dielectric layer in the second region. The method may include forming a second electrode layer. The portion of the second electrode layer in the first region may be separated from the portion of the second electrode layer in the second region. In the second region, the first electrode layer may be connected with the second electrode layer.

Abstract: In certain aspects, a semiconductor device includes a vertical transistor, a metal bit line, and a pad layer. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The metal bit line extends in a second direction perpendicular to the first direction and coupled to a terminal of the vertical transistor via an ohmic contact. The pad layer is positioned between the gate electrode and the metal bit line in the first direction. The gate dielectric and the pad layer have different dielectric materials.

Abstract: A semiconductor device, a memory system, and a fabricating method are provided. The semiconductor device comprises a memory structure bonded with a circuit structure. The memory structure comprises: first transistors each comprising a semiconductor body extending in a vertical direction, a semiconductor layer on a lateral side of the first transistors, a first isolation structure extending through the semiconductor layer and laterally encircling a first portion of the semiconductor layer, a first contact structure extending through the first portion of the semiconductor layer, and a first contact pad above the first portion of the semiconductor layer and connected with the first contact structure. A lateral dimension of the first contact pad is less than a lateral dimension of the first portion of the semiconductor layer. The circuit structure comprises a second transistor, and the first contact pad is electrically connected to the second transistor by the first contact structure.

Abstract: A memory device includes an array of memory cells, bit lines coupled to the memory cells, first air gaps, and second air gaps. Each of the memory cells includes a vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction. Each of the bit lines is connected to a first end of the semiconductor body. At least one of the first air gaps is between adjacent bit lines. At least one of the second air gaps is between adjacent semiconductor bodies of adjacent memory cells.

Abstract: A semiconductor device and methods for forming the same are provided. The method includes: forming a plurality of first trenches having a first width during forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction; forming a spacer in each groove, where the spacer is laterally extending along the first lateral direction; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction.

Abstract: There are provided a wavelength selective switch device, a communication apparatus and a wavelength switching method. The wavelength selective switch device includes an incidence unit; an exit unit; a wavelength diversifying-synthesizing unit for diversifying and multiplexing the respective incident lights in a first axis direction; a light adjustment unit for making the lights of respective wavelengths be not diversified in the second axis direction; a liquid crystal beam deflection unit having a plurality of pixels divided into sub-regions, for deflecting the lights of the respective wavelengths by changing phase-shift characteristics of the pixels in the sub-regions; a reflection unit, disposed in parallel with the liquid crystal beam deflection unit; a deflection driving unit for driving electrodes of the pixels to generate required phase-shift characteristics.