Patents by Inventor Zicheng G. Ling

Zicheng G. Ling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10289784
    Abstract: The disclosed approaches process a circuit design that specifies a clock signal. A plurality of wire segments of an integrated circuit (IC) are selected for a clock path to carry the clock signal. A delay of the clock path is determined based on delay values associated with identifiers of the wire segments and variation factors. Configuration data is generated from the circuit design once the delay of the clock path satisfies a timing constraint, and a circuit is generated from the configuration data to implement a circuit according to the circuit design.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: May 14, 2019
    Assignee: XILINX, INC.
    Inventors: Chiao K. Hwang, Zicheng G. Ling, Nagaraj Savithri
  • Patent number: 7724016
    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: May 25, 2010
    Assignee: Xilinx, Inc.
    Inventors: Xiao-Jie Yuan, Michael J. Hart, Zicheng G. Ling, Steven P. Young
  • Publication number: 20090121737
    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
    Type: Application
    Filed: January 19, 2009
    Publication date: May 14, 2009
    Applicant: XILINX, INC.
    Inventors: Xiao-Jie Yuan, Michael J. Hart, Zicheng G. Ling, Steven P. Young
  • Patent number: 7489152
    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: February 10, 2009
    Assignee: Xilinx, Inc.
    Inventors: Xiao-Jie Yuan, Michael J. Hart, Zicheng G. Ling, Steven P. Young
  • Patent number: 7109734
    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: September 19, 2006
    Assignee: Xilinx, Inc.
    Inventors: Xiao-Jie Yuan, Michael J. Hart, Zicheng G. Ling, Steven P. Young
  • Patent number: 6867580
    Abstract: A test circuit is included in an IC wafer for testing the reliability of ICS under high current stress. The test circuit includes two sensing transistors, a select transistor, and a resistor. The two ends of the resistor are coupled to two sense terminals through the two sensing transistors. One end of the resistor is also coupled to a first stress input terminal; the other end of the resistor is coupled to a second stress input terminal through the select transistor. When the test circuit is selected, the sensing and select transistors are turned on. A current path is formed between the two stress input terminals, and a voltage differential can be measured across the resistor using the two sense terminals. Row and column select circuits enable the rapid testing of many resistor sizes and configurations in an array of such test circuits.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: March 15, 2005
    Assignee: Xilinx, Inc.
    Inventors: Jan L. de Jong, Zicheng G. Ling
  • Patent number: 6842019
    Abstract: A method of testing reliability in an integrated circuit including an array of test circuits, each test circuit including a resistor. The method includes selecting a first test circuit from the array, measuring a pre-stress resistance value for the resistor in the selected test circuit, applying a high stress current across the resistor, removing the high stress current, and measuring a post-stress resistance value for the resistor. Other embodiments include measuring additional resistance values before applying and after removing the high stress current. One embodiment includes applying a positive voltage to one stress input terminal, and then testing a short sensing terminal for the positive voltage, both before and after applying the high stress current. These steps test for whether or not the high stress current has created a short in the test circuit.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: January 11, 2005
    Assignee: XILINX, Inc.
    Inventors: Jan L. de Jong, Zicheng G. Ling
  • Patent number: 6727710
    Abstract: A test circuit is included in an IC wafer for testing the reliability of ICs under high current stress. The test circuit includes two sensing transistors, a select transistor, and a resistor. The two ends of the resistor are coupled to two sense terminals through the two sensing transistors. One end of the resistor is also coupled to a first stress input terminal; the other end of the resistor is coupled to a second stress input terminal through the select transistor. When the test circuit is selected, the sensing and select transistors are turned on. A current path is formed between the two stress input terminals, and a voltage differential can be measured across the resistor using the two sense terminals. Row and column select circuits enable the rapid testing of many resistor sizes and configurations in an array of such test circuits.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: April 27, 2004
    Assignee: Xilinx, Inc.
    Inventors: Jan L. de Jong, Zicheng G. Ling
  • Patent number: 6166558
    Abstract: The invention provides a method and apparatus for calculating gate length and source/drain gate overlap, by measuring gate capacitance. The invention uses previously known fringe capacitance C.sub.fr and unit capacitance C.sub.OX. The invention measures gate capacitance C.sub.g, when the gate is accumulatively biased, and solves for overlap capacitance C.sub.OV using the equation C.sub.OV =(C.sub.g -2C.sub.fr)/2 or C.sub.OV =(C.sub.gg -C.sub.gb -2C.sub.fr)/2. The invention then measures the gate capacitance C.sub.g when the gate to source/drain voltage is set to inversion bias and a zero voltage is applied between the source/drain and the substrate, and solves for the channel capacitance C.sub.ch using the equation C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV. The invention calculates the channel capacitance C.sub.ch where C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV and then calculates gate length where gate length L.sub.g =(2C.sub.OV +C.sub.ch)/C.sub.OX and the effective gate length L.sub.eff =C.sub.ch /C.sub.OX.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: December 26, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chun Jiang, Wei Long, Zicheng G. Ling, Yowjuang W. Liu